Line data Source code
1 0 : /*
2 : * Copyright (c) 2017 Linaro Limited
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
9 :
10 : #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h>
11 :
12 : /* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
13 :
14 : /**
15 : * @brief Pin modes
16 : */
17 :
18 1 : #define STM32_AF0 0x0
19 0 : #define STM32_AF1 0x1
20 0 : #define STM32_AF2 0x2
21 0 : #define STM32_AF3 0x3
22 0 : #define STM32_AF4 0x4
23 0 : #define STM32_AF5 0x5
24 0 : #define STM32_AF6 0x6
25 0 : #define STM32_AF7 0x7
26 0 : #define STM32_AF8 0x8
27 0 : #define STM32_AF9 0x9
28 0 : #define STM32_AF10 0xa
29 0 : #define STM32_AF11 0xb
30 0 : #define STM32_AF12 0xc
31 0 : #define STM32_AF13 0xd
32 0 : #define STM32_AF14 0xe
33 0 : #define STM32_AF15 0xf
34 0 : #define STM32_ANALOG 0x10
35 0 : #define STM32_GPIO 0x11
36 :
37 : /**
38 : * @brief Macro to generate pinmux int using port, pin number and mode arguments
39 : * This is inspired from Linux equivalent st,stm32f429-pinctrl binding
40 : */
41 :
42 1 : #define STM32_MODE_SHIFT 0U
43 0 : #define STM32_MODE_MASK 0x1FU
44 0 : #define STM32_LINE_SHIFT 5U
45 0 : #define STM32_LINE_MASK 0xFU
46 0 : #define STM32_PORT_SHIFT 9U
47 0 : #define STM32_PORT_MASK 0x1FU
48 :
49 : /**
50 : * @brief Pin configuration configuration bit field.
51 : *
52 : * Fields:
53 : *
54 : * - mode [ 0 : 4 ]
55 : * - line [ 5 : 8 ]
56 : * - port [ 9 : 13 ]
57 : *
58 : * @param port Port ('A'..'Q', 'Z')
59 : * @param line Pin (0..15)
60 : * @param mode Mode (ANALOG, GPIO_IN, ALTERNATE).
61 : */
62 1 : #define STM32_PINMUX(port, line, mode) \
63 : (((((port) - 'A') & STM32_PORT_MASK) << STM32_PORT_SHIFT) | \
64 : (((line) & STM32_LINE_MASK) << STM32_LINE_SHIFT) | \
65 : (((STM32_ ## mode) & STM32_MODE_MASK) << STM32_MODE_SHIFT))
66 :
67 : /**
68 : * @brief PIN configuration bitfield
69 : *
70 : * Pin configuration is coded with the following
71 : * fields
72 : * [03:00] Alternate Functions
73 : * [05:04] GPIO Mode
74 : * [ 06] GPIO Output type
75 : * [08:07] GPIO Speed
76 : * [10:09] GPIO PUPD config
77 : * [ 11] GPIO Output data
78 : *
79 : * These fields are only used when pinctrl with compatible
80 : * "st,stm32n6-pinctrl" is in use:
81 : * [15:12] I/O delay length
82 : * [ 16] I/O delay direction
83 : * [18:17] I/O retime edge
84 : * [ 19] I/O retime enable
85 : *
86 : * NOTE: the values for these fields are not defined in this file
87 : * because they depend on hardware definitions. The values can be
88 : * found in `soc/st/stm32/common/pinctrl_soc.h` instead.
89 : */
90 :
91 : /* GPIO Mode */
92 1 : #define STM32_MODER_INPUT_MODE (0x0 << STM32_MODER_SHIFT)
93 0 : #define STM32_MODER_OUTPUT_MODE (0x1 << STM32_MODER_SHIFT)
94 0 : #define STM32_MODER_ALT_MODE (0x2 << STM32_MODER_SHIFT)
95 0 : #define STM32_MODER_ANALOG_MODE (0x3 << STM32_MODER_SHIFT)
96 0 : #define STM32_MODER_MASK 0x3
97 0 : #define STM32_MODER_SHIFT 4
98 :
99 : /* GPIO Output type */
100 0 : #define STM32_OTYPER_PUSH_PULL (0x0 << STM32_OTYPER_SHIFT)
101 0 : #define STM32_OTYPER_OPEN_DRAIN (0x1 << STM32_OTYPER_SHIFT)
102 0 : #define STM32_OTYPER_MASK 0x1
103 0 : #define STM32_OTYPER_SHIFT 6
104 :
105 : /* GPIO speed */
106 0 : #define STM32_OSPEEDR_LOW_SPEED (0x0 << STM32_OSPEEDR_SHIFT)
107 0 : #define STM32_OSPEEDR_MEDIUM_SPEED (0x1 << STM32_OSPEEDR_SHIFT)
108 0 : #define STM32_OSPEEDR_HIGH_SPEED (0x2 << STM32_OSPEEDR_SHIFT)
109 0 : #define STM32_OSPEEDR_VERY_HIGH_SPEED (0x3 << STM32_OSPEEDR_SHIFT)
110 0 : #define STM32_OSPEEDR_MASK 0x3
111 0 : #define STM32_OSPEEDR_SHIFT 7
112 :
113 : /* GPIO High impedance/Pull-up/pull-down */
114 0 : #define STM32_PUPDR_NO_PULL (0x0 << STM32_PUPDR_SHIFT)
115 0 : #define STM32_PUPDR_PULL_UP (0x1 << STM32_PUPDR_SHIFT)
116 0 : #define STM32_PUPDR_PULL_DOWN (0x2 << STM32_PUPDR_SHIFT)
117 0 : #define STM32_PUPDR_MASK 0x3
118 0 : #define STM32_PUPDR_SHIFT 9
119 :
120 : /* GPIO plain output value */
121 0 : #define STM32_ODR_0 (0x0 << STM32_ODR_SHIFT)
122 0 : #define STM32_ODR_1 (0x1 << STM32_ODR_SHIFT)
123 0 : #define STM32_ODR_MASK 0x1
124 0 : #define STM32_ODR_SHIFT 11
125 :
126 : /* I/O delay length (DELAYR) */
127 0 : #define STM32_IODELAY_LENGTH_MASK 0xFU
128 0 : #define STM32_IODELAY_LENGTH_SHIFT 12
129 :
130 : /* I/O delay & retime configuration (ADVCFGR) */
131 0 : #define STM32_IORETIME_ADVCFGR_MASK 0xFU
132 0 : #define STM32_IORETIME_ADVCFGR_SHIFT 16
133 :
134 0 : #define STM32_IODELAY_DIRECTION_SHIFT STM32_IORETIME_ADVCFGR_SHIFT
135 0 : #define STM32_IORETIME_EDGE_SHIFT 17
136 0 : #define STM32_IORETIME_ENABLE_SHIFT 19
137 :
138 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_ */
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