LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/pinctrl - xmc4xxx-pinctrl.h Coverage Total Hit
Test: new.info Lines: 0.0 % 38 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2022 Schlumberger
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_XMC4XXX_PINCTRL_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_XMC4XXX_PINCTRL_H_
       9              : 
      10              : /* Bit Masks */
      11              : 
      12            0 : #define XMC4XXX_PORT_POS        0
      13            0 : #define XMC4XXX_PORT_MASK       0xf
      14              : 
      15            0 : #define XMC4XXX_PIN_POS         4
      16            0 : #define XMC4XXX_PIN_MASK        0xf
      17              : 
      18            0 : #define XMC4XXX_ALT_POS         8
      19            0 : #define XMC4XXX_ALT_MASK        0xf
      20              : 
      21            0 : #define XMC4XXX_PULL_DOWN_POS   12
      22            0 : #define XMC4XXX_PULL_DOWN_MASK  0x1
      23              : 
      24            0 : #define XMC4XXX_PULL_UP_POS     13
      25            0 : #define XMC4XXX_PULL_UP_MASK    0x1
      26              : 
      27            0 : #define XMC4XXX_PUSH_PULL_POS   14
      28            0 : #define XMC4XXX_PUSH_PULL_MASK  0x1
      29              : 
      30            0 : #define XMC4XXX_OPEN_DRAIN_POS  15
      31            0 : #define XMC4XXX_OPEN_DRAIN_MASK 0x1
      32              : 
      33            0 : #define XMC4XXX_OUT_HIGH_POS    16
      34            0 : #define XMC4XXX_OUT_HIGH_MASK   0x1
      35              : 
      36            0 : #define XMC4XXX_OUT_LOW_POS     17
      37            0 : #define XMC4XXX_OUT_LOW_MASK    0x1
      38              : 
      39            0 : #define XMC4XXX_INV_INPUT_POS   18
      40            0 : #define XMC4XXX_INV_INPUT_MASK  0x1
      41              : 
      42            0 : #define XMC4XXX_DRIVE_POS       19
      43            0 : #define XMC4XXX_DRIVE_MASK      0x7
      44              : 
      45            0 : #define XMC4XXX_HWCTRL_POS      22
      46            0 : #define XMC4XXX_HWCTRL_MASK     0x3
      47              : 
      48              : /* Setters and getters */
      49              : 
      50            0 : #define XMC4XXX_PINMUX_SET(port, pin, alt_fun)                                                     \
      51              :         ((port) << XMC4XXX_PORT_POS | (pin) << XMC4XXX_PIN_POS | (alt_fun) << XMC4XXX_ALT_POS)
      52              : 
      53            0 : #define XMC4XXX_PINMUX_GET_PORT(mx)           ((mx >> XMC4XXX_PORT_POS)       & XMC4XXX_PORT_MASK)
      54            0 : #define XMC4XXX_PINMUX_GET_PIN(mx)            ((mx >> XMC4XXX_PIN_POS)        & XMC4XXX_PIN_MASK)
      55            0 : #define XMC4XXX_PINMUX_GET_ALT(mx)            ((mx >> XMC4XXX_ALT_POS)        & XMC4XXX_ALT_MASK)
      56            0 : #define XMC4XXX_PINMUX_GET_PULL_DOWN(mx)  ((mx >> XMC4XXX_PULL_DOWN_POS)  & XMC4XXX_PULL_DOWN_MASK)
      57            0 : #define XMC4XXX_PINMUX_GET_PULL_UP(mx)    ((mx >> XMC4XXX_PULL_UP_POS)    & XMC4XXX_PULL_UP_MASK)
      58            0 : #define XMC4XXX_PINMUX_GET_PUSH_PULL(mx)  ((mx >> XMC4XXX_PUSH_PULL_POS)  & XMC4XXX_PUSH_PULL_MASK)
      59            0 : #define XMC4XXX_PINMUX_GET_OPEN_DRAIN(mx) ((mx >> XMC4XXX_OPEN_DRAIN_POS) & XMC4XXX_OPEN_DRAIN_MASK)
      60            0 : #define XMC4XXX_PINMUX_GET_OUT_HIGH(mx)   ((mx >> XMC4XXX_OUT_HIGH_POS)   & XMC4XXX_OUT_HIGH_MASK)
      61            0 : #define XMC4XXX_PINMUX_GET_OUT_LOW(mx)    ((mx >> XMC4XXX_OUT_LOW_POS)    & XMC4XXX_OUT_LOW_MASK)
      62            0 : #define XMC4XXX_PINMUX_GET_INV_INPUT(mx)  ((mx >> XMC4XXX_INV_INPUT_POS)  & XMC4XXX_INV_INPUT_MASK)
      63            0 : #define XMC4XXX_PINMUX_GET_DRIVE(mx)      ((mx >> XMC4XXX_DRIVE_POS)      & XMC4XXX_DRIVE_MASK)
      64            0 : #define XMC4XXX_PINMUX_GET_HWCTRL(mx)     ((mx >> XMC4XXX_HWCTRL_POS)     & XMC4XXX_HWCTRL_MASK)
      65              : 
      66              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_XMC4XXX_PINCTRL_H_ */
        

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