Line data Source code
1 0 : /*
2 : * Copyright (c) 2021, NXP
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 :
8 : /*
9 : * Setpoint definitions for IMX Set point controller. The SPC uses a series
10 : * of set points to determine the clock speeds and states of cores, as well
11 : * as which peripherals to gate clocks to. Higher values correspond to more
12 : * power saving. See your SOC's datasheet for specifics of what peripherals
13 : * have their clocks gated at each set point.
14 : *
15 : * Set point control is implemented at the soc level (see pm_state_set())
16 : */
17 :
18 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
19 : #define ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_
20 :
21 0 : #define IMX_GPC_RUN 0x0
22 0 : #define IMX_GPC_WAIT 0x1
23 0 : #define IMX_GPC_STOP 0x2
24 0 : #define IMX_GPC_SUSPEND 0x3
25 :
26 :
27 0 : #define IMX_SPC_MASK 0xF0
28 0 : #define IMX_SPC_SHIFT 4
29 0 : #define IMX_GPC_MODE_MASK 0xF
30 :
31 0 : #define IMX_SPC(x) ((x & IMX_SPC_MASK) >> IMX_SPC_SHIFT)
32 0 : #define IMX_GPC_MODE(x) (x & IMX_GPC_MODE_MASK)
33 :
34 0 : #define IMX_SPC_0 0x00
35 0 : #define IMX_SPC_1 0x10
36 0 : #define IMX_SPC_2 0x20
37 0 : #define IMX_SPC_3 0x30
38 0 : #define IMX_SPC_4 0x40
39 0 : #define IMX_SPC_5 0x50
40 0 : #define IMX_SPC_6 0x60
41 0 : #define IMX_SPC_7 0x70
42 0 : #define IMX_SPC_8 0x80
43 0 : #define IMX_SPC_9 0x90
44 0 : #define IMX_SPC_10 0xA0
45 0 : #define IMX_SPC_11 0xB0
46 0 : #define IMX_SPC_12 0xC0
47 0 : #define IMX_SPC_13 0xD0
48 0 : #define IMX_SPC_14 0xE0
49 0 : #define IMX_SPC_15 0xF0
50 :
51 :
52 0 : #define IMX_SPC_SET_POINT_0_RUN (IMX_SPC_0 | IMX_GPC_RUN)
53 0 : #define IMX_SPC_SET_POINT_0_WAIT (IMX_SPC_0 | IMX_GPC_WAIT)
54 0 : #define IMX_SPC_SET_POINT_0_STOP (IMX_SPC_0 | IMX_GPC_STOP)
55 0 : #define IMX_SPC_SET_POINT_0_SUSPEND (IMX_SPC_0 | IMX_GPC_SUSPEND)
56 0 : #define IMX_SPC_SET_POINT_1_RUN (IMX_SPC_1 | IMX_GPC_RUN)
57 0 : #define IMX_SPC_SET_POINT_1_WAIT (IMX_SPC_1 | IMX_GPC_WAIT)
58 0 : #define IMX_SPC_SET_POINT_1_STOP (IMX_SPC_1 | IMX_GPC_STOP)
59 0 : #define IMX_SPC_SET_POINT_1_SUSPEND (IMX_SPC_1 | IMX_GPC_SUSPEND)
60 0 : #define IMX_SPC_SET_POINT_2_RUN (IMX_SPC_2 | IMX_GPC_RUN)
61 0 : #define IMX_SPC_SET_POINT_2_WAIT (IMX_SPC_2 | IMX_GPC_WAIT)
62 0 : #define IMX_SPC_SET_POINT_2_STOP (IMX_SPC_2 | IMX_GPC_STOP)
63 0 : #define IMX_SPC_SET_POINT_2_SUSPEND (IMX_SPC_2 | IMX_GPC_SUSPEND)
64 0 : #define IMX_SPC_SET_POINT_3_RUN (IMX_SPC_3 | IMX_GPC_RUN)
65 0 : #define IMX_SPC_SET_POINT_3_WAIT (IMX_SPC_3 | IMX_GPC_WAIT)
66 0 : #define IMX_SPC_SET_POINT_3_STOP (IMX_SPC_3 | IMX_GPC_STOP)
67 0 : #define IMX_SPC_SET_POINT_3_SUSPEND (IMX_SPC_3 | IMX_GPC_SUSPEND)
68 0 : #define IMX_SPC_SET_POINT_4_RUN (IMX_SPC_4 | IMX_GPC_RUN)
69 0 : #define IMX_SPC_SET_POINT_4_WAIT (IMX_SPC_4 | IMX_GPC_WAIT)
70 0 : #define IMX_SPC_SET_POINT_4_STOP (IMX_SPC_4 | IMX_GPC_STOP)
71 0 : #define IMX_SPC_SET_POINT_4_SUSPEND (IMX_SPC_4 | IMX_GPC_SUSPEND)
72 0 : #define IMX_SPC_SET_POINT_5_RUN (IMX_SPC_5 | IMX_GPC_RUN)
73 0 : #define IMX_SPC_SET_POINT_5_WAIT (IMX_SPC_5 | IMX_GPC_WAIT)
74 0 : #define IMX_SPC_SET_POINT_5_STOP (IMX_SPC_5 | IMX_GPC_STOP)
75 0 : #define IMX_SPC_SET_POINT_5_SUSPEND (IMX_SPC_5 | IMX_GPC_SUSPEND)
76 0 : #define IMX_SPC_SET_POINT_6_RUN (IMX_SPC_6 | IMX_GPC_RUN)
77 0 : #define IMX_SPC_SET_POINT_6_WAIT (IMX_SPC_6 | IMX_GPC_WAIT)
78 0 : #define IMX_SPC_SET_POINT_6_STOP (IMX_SPC_6 | IMX_GPC_STOP)
79 0 : #define IMX_SPC_SET_POINT_6_SUSPEND (IMX_SPC_6 | IMX_GPC_SUSPEND)
80 0 : #define IMX_SPC_SET_POINT_7_RUN (IMX_SPC_7 | IMX_GPC_RUN)
81 0 : #define IMX_SPC_SET_POINT_7_WAIT (IMX_SPC_7 | IMX_GPC_WAIT)
82 0 : #define IMX_SPC_SET_POINT_7_STOP (IMX_SPC_7 | IMX_GPC_STOP)
83 0 : #define IMX_SPC_SET_POINT_7_SUSPEND (IMX_SPC_7 | IMX_GPC_SUSPEND)
84 0 : #define IMX_SPC_SET_POINT_8_RUN (IMX_SPC_8 | IMX_GPC_RUN)
85 0 : #define IMX_SPC_SET_POINT_8_WAIT (IMX_SPC_8 | IMX_GPC_WAIT)
86 0 : #define IMX_SPC_SET_POINT_8_STOP (IMX_SPC_8 | IMX_GPC_STOP)
87 0 : #define IMX_SPC_SET_POINT_8_SUSPEND (IMX_SPC_8 | IMX_GPC_SUSPEND)
88 0 : #define IMX_SPC_SET_POINT_9_RUN (IMX_SPC_9 | IMX_GPC_RUN)
89 0 : #define IMX_SPC_SET_POINT_9_WAIT (IMX_SPC_9 | IMX_GPC_WAIT)
90 0 : #define IMX_SPC_SET_POINT_9_STOP (IMX_SPC_9 | IMX_GPC_STOP)
91 0 : #define IMX_SPC_SET_POINT_9_SUSPEND (IMX_SPC_9 | IMX_GPC_SUSPEND)
92 0 : #define IMX_SPC_SET_POINT_10_RUN (IMX_SPC_10 | IMX_GPC_RUN)
93 0 : #define IMX_SPC_SET_POINT_10_WAIT (IMX_SPC_10 | IMX_GPC_WAIT)
94 0 : #define IMX_SPC_SET_POINT_10_STOP (IMX_SPC_10 | IMX_GPC_STOP)
95 0 : #define IMX_SPC_SET_POINT_10_SUSPEND (IMX_SPC_10 | IMX_GPC_SUSPEND)
96 0 : #define IMX_SPC_SET_POINT_11_RUN (IMX_SPC_11 | IMX_GPC_RUN)
97 0 : #define IMX_SPC_SET_POINT_11_WAIT (IMX_SPC_11 | IMX_GPC_WAIT)
98 0 : #define IMX_SPC_SET_POINT_11_STOP (IMX_SPC_11 | IMX_GPC_STOP)
99 0 : #define IMX_SPC_SET_POINT_11_SUSPEND (IMX_SPC_11 | IMX_GPC_SUSPEND)
100 0 : #define IMX_SPC_SET_POINT_12_RUN (IMX_SPC_12 | IMX_GPC_RUN)
101 0 : #define IMX_SPC_SET_POINT_12_WAIT (IMX_SPC_12 | IMX_GPC_WAIT)
102 0 : #define IMX_SPC_SET_POINT_12_STOP (IMX_SPC_12 | IMX_GPC_STOP)
103 0 : #define IMX_SPC_SET_POINT_12_SUSPEND (IMX_SPC_12 | IMX_GPC_SUSPEND)
104 0 : #define IMX_SPC_SET_POINT_13_RUN (IMX_SPC_13 | IMX_GPC_RUN)
105 0 : #define IMX_SPC_SET_POINT_13_WAIT (IMX_SPC_13 | IMX_GPC_WAIT)
106 0 : #define IMX_SPC_SET_POINT_13_STOP (IMX_SPC_13 | IMX_GPC_STOP)
107 0 : #define IMX_SPC_SET_POINT_13_SUSPEND (IMX_SPC_13 | IMX_GPC_SUSPEND)
108 0 : #define IMX_SPC_SET_POINT_14_RUN (IMX_SPC_14 | IMX_GPC_RUN)
109 0 : #define IMX_SPC_SET_POINT_14_WAIT (IMX_SPC_14 | IMX_GPC_WAIT)
110 0 : #define IMX_SPC_SET_POINT_14_STOP (IMX_SPC_14 | IMX_GPC_STOP)
111 0 : #define IMX_SPC_SET_POINT_14_SUSPEND (IMX_SPC_14 | IMX_GPC_SUSPEND)
112 0 : #define IMX_SPC_SET_POINT_15_RUN (IMX_SPC_15 | IMX_GPC_RUN)
113 0 : #define IMX_SPC_SET_POINT_15_WAIT (IMX_SPC_15 | IMX_GPC_WAIT)
114 0 : #define IMX_SPC_SET_POINT_15_STOP (IMX_SPC_15 | IMX_GPC_STOP)
115 0 : #define IMX_SPC_SET_POINT_15_SUSPEND (IMX_SPC_15 | IMX_GPC_SUSPEND)
116 :
117 :
118 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ */
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