Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Aspeed Technology Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
       9              : 
      10            0 : #define ASPEED_RESET_GRP_0_OFFSET       (0)
      11            0 : #define ASPEED_RESET_GRP_1_OFFSET       (32)
      12              : 
      13            0 : #define ASPEED_RESET_HACE               (ASPEED_RESET_GRP_0_OFFSET + 4)
      14            0 : #define ASPEED_RESET_USB                (ASPEED_RESET_GRP_0_OFFSET + 3)
      15            0 : #define ASPEED_RESET_SRAM               (ASPEED_RESET_GRP_0_OFFSET + 0)
      16              : 
      17            0 : #define ASPEED_RESET_UART4              (ASPEED_RESET_GRP_1_OFFSET + 31)
      18            0 : #define ASPEED_RESET_UART3              (ASPEED_RESET_GRP_1_OFFSET + 30)
      19            0 : #define ASPEED_RESET_UART2              (ASPEED_RESET_GRP_1_OFFSET + 29)
      20            0 : #define ASPEED_RESET_UART1              (ASPEED_RESET_GRP_1_OFFSET + 28)
      21              : 
      22            0 : #define ASPEED_RESET_JTAG_M0            (ASPEED_RESET_GRP_1_OFFSET + 26)
      23            0 : #define ASPEED_RESET_ESPI               (ASPEED_RESET_GRP_1_OFFSET + 25)
      24              : 
      25            0 : #define ASPEED_RESET_ADC                (ASPEED_RESET_GRP_1_OFFSET + 23)
      26            0 : #define ASPEED_RESET_JTAG_M1            (ASPEED_RESET_GRP_1_OFFSET + 22)
      27              : 
      28            0 : #define ASPEED_RESET_MAC                (ASPEED_RESET_GRP_1_OFFSET + 20)
      29              : 
      30            0 : #define ASPEED_RESET_I3C3               (ASPEED_RESET_GRP_1_OFFSET + 11)
      31            0 : #define ASPEED_RESET_I3C2               (ASPEED_RESET_GRP_1_OFFSET + 10)
      32            0 : #define ASPEED_RESET_I3C1               (ASPEED_RESET_GRP_1_OFFSET + 9)
      33            0 : #define ASPEED_RESET_I3C0               (ASPEED_RESET_GRP_1_OFFSET + 8)
      34            0 : #define ASPEED_RESET_I3C                (ASPEED_RESET_GRP_1_OFFSET + 7)
      35            0 : #define ASPEED_RESET_PWM_TACH           (ASPEED_RESET_GRP_1_OFFSET + 5)
      36            0 : #define ASPEED_RESET_PECI               (ASPEED_RESET_GRP_1_OFFSET + 4)
      37            0 : #define ASPEED_RESET_MII                (ASPEED_RESET_GRP_1_OFFSET + 3)
      38            0 : #define ASPEED_RESET_I2C                (ASPEED_RESET_GRP_1_OFFSET + 2)
      39              : 
      40            0 : #define ASPEED_RESET_LPC                (ASPEED_RESET_GRP_1_OFFSET + 0)
      41              : 
      42              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ */