Line data    Source code

       1            0 : /*
       2              :  * Copyright (C) 2025 embedded brains GmbH & Co. KG
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
       9              : 
      10              : /*
      11              :  * The reset ID encodes the bit index of the SUBBLK_CLOCK_CR and SOFT_RESET_CR
      12              :  * registers associated with the device.
      13              :  */
      14            0 : #define MSS_RESET_ID_ENVM    0x0
      15            0 : #define MSS_RESET_ID_MAC0    0x1
      16            0 : #define MSS_RESET_ID_MAC1    0x2
      17            0 : #define MSS_RESET_ID_MMC     0x3
      18            0 : #define MSS_RESET_ID_TIMER   0x4
      19            0 : #define MSS_RESET_ID_MMUART0 0x5
      20            0 : #define MSS_RESET_ID_MMUART1 0x6
      21            0 : #define MSS_RESET_ID_MMUART2 0x7
      22            0 : #define MSS_RESET_ID_MMUART3 0x8
      23            0 : #define MSS_RESET_ID_MMUART4 0x9
      24            0 : #define MSS_RESET_ID_SPI0    0xa
      25            0 : #define MSS_RESET_ID_SPI1    0xb
      26            0 : #define MSS_RESET_ID_I2C0    0xc
      27            0 : #define MSS_RESET_ID_I2C1    0xd
      28            0 : #define MSS_RESET_ID_CAN0    0xe
      29            0 : #define MSS_RESET_ID_CAN1    0xf
      30            0 : #define MSS_RESET_ID_USB     0x10
      31            0 : #define MSS_RESET_ID_RSVD    0x11
      32            0 : #define MSS_RESET_ID_RTC     0x12
      33            0 : #define MSS_RESET_ID_QSPI    0x13
      34            0 : #define MSS_RESET_ID_GPIO0   0x14
      35            0 : #define MSS_RESET_ID_GPIO1   0x15
      36            0 : #define MSS_RESET_ID_GPIO2   0x16
      37            0 : #define MSS_RESET_ID_DDRC    0x17
      38            0 : #define MSS_RESET_ID_FIC0    0x18
      39            0 : #define MSS_RESET_ID_FIC1    0x19
      40            0 : #define MSS_RESET_ID_FIC2    0x1a
      41            0 : #define MSS_RESET_ID_FIC3    0x1b
      42            0 : #define MSS_RESET_ID_ATHENA  0x1c
      43            0 : #define MSS_RESET_ID_CFM     0x1d
      44              : 
      45              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_ */