Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Nuvoton Technology Corporation.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
9 :
10 0 : #define NPCX_RESET_SWRST_CTL1_OFFSET 0
11 0 : #define NPCX_RESET_SWRST_CTL2_OFFSET 32
12 0 : #define NPCX_RESET_SWRST_CTL3_OFFSET 64
13 0 : #define NPCX_RESET_SWRST_CTL4_OFFSET 96
14 :
15 0 : #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
16 0 : #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
17 0 : #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
18 0 : #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
19 0 : #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
20 0 : #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
21 0 : #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
22 0 : #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
23 0 : #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
24 0 : #define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
25 0 : #define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
26 0 : #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
27 0 : #define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
28 0 : #define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
29 0 : #define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
30 0 : #define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
31 0 : #define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
32 0 : #define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
33 0 : #define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
34 0 : #define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
35 0 : #define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
36 0 : #define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
37 0 : #define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
38 0 : #define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
39 0 : #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
40 0 : #define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
41 0 : #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
42 0 : #define NPCX_RESET_GDMA1 (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
43 0 : #define NPCX_RESET_GDMA2 (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
44 :
45 0 : #define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
46 0 : #define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
47 0 : #define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
48 0 : #define NPCX_RESET_ADCE (NPCX_RESET_SWRST_CTL2_OFFSET + 4)
49 0 : #define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
50 0 : #define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
51 0 : #define NPCX_RESET_ADCI (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
52 0 : #define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
53 0 : #define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
54 0 : #define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
55 0 : #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
56 0 : #define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
57 0 : #define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
58 0 : #define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
59 0 : #define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
60 0 : #define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
61 0 : #define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
62 0 : #define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
63 0 : #define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
64 0 : #define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
65 0 : #define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
66 0 : #define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
67 0 : #define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
68 0 : #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
69 0 : #define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
70 0 : #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
71 0 : #define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
72 0 : #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
73 0 : #define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
74 0 : #define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
75 0 : #define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
76 :
77 0 : #define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
78 0 : #define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
79 0 : #define NPCX_RESET_I3C_1 (NPCX_RESET_SWRST_CTL3_OFFSET + 4)
80 0 : #define NPCX_RESET_I3C_2 (NPCX_RESET_SWRST_CTL3_OFFSET + 5)
81 0 : #define NPCX_RESET_I3C_3 (NPCX_RESET_SWRST_CTL3_OFFSET + 6)
82 0 : #define NPCX_RESET_I3C_RD (NPCX_RESET_SWRST_CTL3_OFFSET + 7)
83 0 : #define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
84 0 : #define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
85 0 : #define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
86 0 : #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
87 0 : #define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
88 0 : #define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
89 0 : #define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
90 0 : #define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
91 0 : #define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18)
92 0 : #define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19)
93 0 : #define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
94 0 : #define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
95 0 : #define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
96 0 : #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
97 0 : #define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
98 0 : #define NPCX_RESET_SHA_2B (NPCX_RESET_SWRST_CTL3_OFFSET + 26)
99 0 : #define NPCX_RESET_SHA_2A (NPCX_RESET_SWRST_CTL3_OFFSET + 29)
100 :
101 0 : #define NPCX_RESET_MDC (NPCX_RESET_SWRST_CTL4_OFFSET + 15)
102 0 : #define NPCX_RESET_FIU0 (NPCX_RESET_SWRST_CTL4_OFFSET + 16)
103 0 : #define NPCX_RESET_FIU1 (NPCX_RESET_SWRST_CTL4_OFFSET + 17)
104 0 : #define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24)
105 0 : #define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25)
106 0 : #define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26)
107 0 : #define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27)
108 0 : #define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28)
109 0 : #define NPCX_RESET_MDMA6 (NPCX_RESET_SWRST_CTL4_OFFSET + 29)
110 0 : #define NPCX_RESET_MDMA7 (NPCX_RESET_SWRST_CTL4_OFFSET + 30)
111 :
112 0 : #define NPCX_RESET_ID_START NPCX_RESET_GPIO0
113 0 : #define NPCX_RESET_ID_END NPCX_RESET_MDMA7
114 : #endif
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