Line data Source code
1 0 : /* 2 : * Copyright (c) 2024 Nuvoton Technology Corporation. 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H 8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H 9 : 10 0 : #define NPCX_RESET_SWRST_CTL1_OFFSET 0 11 0 : #define NPCX_RESET_SWRST_CTL2_OFFSET 32 12 0 : #define NPCX_RESET_SWRST_CTL3_OFFSET 64 13 : 14 0 : #define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0) 15 0 : #define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1) 16 0 : #define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2) 17 0 : #define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3) 18 0 : #define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4) 19 0 : #define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5) 20 0 : #define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6) 21 0 : #define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7) 22 0 : #define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8) 23 0 : #define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9) 24 0 : #define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10) 25 0 : #define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11) 26 0 : #define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12) 27 0 : #define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13) 28 0 : #define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14) 29 0 : #define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15) 30 0 : #define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16) 31 0 : #define NPCX_RESET_ITIM16_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18) 32 0 : #define NPCX_RESET_ITIM16_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19) 33 0 : #define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20) 34 0 : #define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21) 35 0 : #define NPCX_RESET_ITIM16_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22) 36 0 : #define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23) 37 0 : #define NPCX_RESET_ITIM32 (NPCX_RESET_SWRST_CTL1_OFFSET + 24) 38 0 : #define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25) 39 0 : #define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26) 40 0 : #define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27) 41 0 : #define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28) 42 0 : #define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29) 43 0 : #define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30) 44 : 45 0 : #define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0) 46 0 : #define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2) 47 0 : #define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3) 48 0 : #define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5) 49 0 : #define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6) 50 0 : #define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7) 51 0 : #define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8) 52 0 : #define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9) 53 0 : #define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10) 54 0 : #define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11) 55 0 : #define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12) 56 0 : #define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13) 57 0 : #define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14) 58 0 : #define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15) 59 0 : #define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16) 60 0 : #define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17) 61 0 : #define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18) 62 0 : #define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19) 63 0 : #define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20) 64 0 : #define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21) 65 0 : #define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22) 66 0 : #define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23) 67 0 : #define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24) 68 0 : #define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25) 69 0 : #define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26) 70 0 : #define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27) 71 0 : #define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28) 72 0 : #define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29) 73 0 : #define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30) 74 0 : #define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31) 75 : 76 0 : #define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0) 77 0 : #define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1) 78 0 : #define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8) 79 0 : #define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9) 80 0 : #define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10) 81 0 : #define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11) 82 0 : #define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12) 83 0 : #define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13) 84 0 : #define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15) 85 0 : #define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16) 86 0 : #define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20) 87 0 : #define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22) 88 0 : #define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23) 89 0 : #define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24) 90 0 : #define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25) 91 : 92 0 : #define NPCX_RESET_ID_START NPCX_RESET_GPIO0 93 0 : #define NPCX_RESET_ID_END NPCX_RESET_BBRAM 94 : #endif
