Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Nuvoton Technology Corporation.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
9 :
10 : /* Beginning of M2L31 BSP sys_reg.h reset module copy */
11 :
12 0 : #define LPSCC_IPRST0_LPPDMA0RST_Pos 0
13 0 : #define LPSCC_IPRST0_LPGPIORST_Pos 1
14 0 : #define LPSCC_IPRST0_LPSRAMRST_Pos 2
15 0 : #define LPSCC_IPRST0_WDTRST_Pos 16
16 0 : #define LPSCC_IPRST0_LPSPI0RST_Pos 17
17 0 : #define LPSCC_IPRST0_LPI2C0RST_Pos 18
18 0 : #define LPSCC_IPRST0_LPUART0RST_Pos 19
19 0 : #define LPSCC_IPRST0_LPTMR0RST_Pos 20
20 0 : #define LPSCC_IPRST0_LPTMR1RST_Pos 21
21 0 : #define LPSCC_IPRST0_TTMR0RST_Pos 22
22 0 : #define LPSCC_IPRST0_TTMR1RST_Pos 23
23 0 : #define LPSCC_IPRST0_LPADC0RST_Pos 24
24 0 : #define LPSCC_IPRST0_OPARST_Pos 27
25 0 : #define SYS_IPRST0_CHIPRST_Pos 0
26 0 : #define SYS_IPRST0_CPURST_Pos 1
27 0 : #define SYS_IPRST0_PDMA0RST_Pos 2
28 0 : #define SYS_IPRST0_EBIRST_Pos 3
29 0 : #define SYS_IPRST0_USBHRST_Pos 4
30 0 : #define SYS_IPRST0_CRCRST_Pos 7
31 0 : #define SYS_IPRST0_CRPTRST_Pos 12
32 0 : #define SYS_IPRST0_CANFD0RST_Pos 20
33 0 : #define SYS_IPRST0_CANFD1RST_Pos 21
34 0 : #define SYS_IPRST1_GPIORST_Pos 1
35 0 : #define SYS_IPRST1_TMR0RST_Pos 2
36 0 : #define SYS_IPRST1_TMR1RST_Pos 3
37 0 : #define SYS_IPRST1_TMR2RST_Pos 4
38 0 : #define SYS_IPRST1_TMR3RST_Pos 5
39 0 : #define SYS_IPRST1_ACMP01RST_Pos 7
40 0 : #define SYS_IPRST1_I2C0RST_Pos 8
41 0 : #define SYS_IPRST1_I2C1RST_Pos 9
42 0 : #define SYS_IPRST1_I2C2RST_Pos 10
43 0 : #define SYS_IPRST1_I2C3RST_Pos 11
44 0 : #define SYS_IPRST1_QSPI0RST_Pos 12
45 0 : #define SYS_IPRST1_SPI0RST_Pos 13
46 0 : #define SYS_IPRST1_SPI1RST_Pos 14
47 0 : #define SYS_IPRST1_SPI2RST_Pos 15
48 0 : #define SYS_IPRST1_UART0RST_Pos 16
49 0 : #define SYS_IPRST1_UART1RST_Pos 17
50 0 : #define SYS_IPRST1_UART2RST_Pos 18
51 0 : #define SYS_IPRST1_UART3RST_Pos 19
52 0 : #define SYS_IPRST1_UART4RST_Pos 20
53 0 : #define SYS_IPRST1_UART5RST_Pos 21
54 0 : #define SYS_IPRST1_UART6RST_Pos 22
55 0 : #define SYS_IPRST1_UART7RST_Pos 23
56 0 : #define SYS_IPRST1_OTGRST_Pos 26
57 0 : #define SYS_IPRST1_USBDRST_Pos 27
58 0 : #define SYS_IPRST1_EADC0RST_Pos 28
59 0 : #define SYS_IPRST1_TRNGRST_Pos 31
60 0 : #define SYS_IPRST2_SPI3RST_Pos 6
61 0 : #define SYS_IPRST2_USCI0RST_Pos 8
62 0 : #define SYS_IPRST2_USCI1RST_Pos 9
63 0 : #define SYS_IPRST2_WWDTRST_Pos 11
64 0 : #define SYS_IPRST2_DACRST_Pos 12
65 0 : #define SYS_IPRST2_EPWM0RST_Pos 16
66 0 : #define SYS_IPRST2_EPWM1RST_Pos 17
67 0 : #define SYS_IPRST2_EQEI0RST_Pos 22
68 0 : #define SYS_IPRST2_EQEI1RST_Pos 23
69 0 : #define SYS_IPRST2_TKRST_Pos 25
70 0 : #define SYS_IPRST2_ECAP0RST_Pos 26
71 0 : #define SYS_IPRST2_ECAP1RST_Pos 27
72 0 : #define SYS_IPRST3_ACMP2RST_Pos 7
73 0 : #define SYS_IPRST3_PWM0RST_Pos 8
74 0 : #define SYS_IPRST3_PWM1RST_Pos 9
75 0 : #define SYS_IPRST3_UTCPD0RST_Pos 15
76 :
77 : /* End of M2L31 BSP sys_reg.h reset module copy */
78 :
79 : /* Beginning of M2L31 BSP sys.h reset module copy */
80 :
81 : /*---------------------------------------------------------------------
82 : * Module Reset Control Resister constant definitions.
83 : *---------------------------------------------------------------------
84 : */
85 :
86 0 : #define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos)
87 0 : #define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)
88 0 : #define NUMAKER_USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos)
89 0 : #define NUMAKER_CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos)
90 0 : #define NUMAKER_CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos)
91 0 : #define NUMAKER_CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos)
92 0 : #define NUMAKER_CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos)
93 :
94 0 : #define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)
95 0 : #define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)
96 0 : #define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)
97 0 : #define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)
98 0 : #define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)
99 0 : #define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)
100 0 : #define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)
101 0 : #define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)
102 0 : #define NUMAKER_I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos)
103 0 : #define NUMAKER_I2C3_RST ((4UL<<24) | SYS_IPRST1_I2C3RST_Pos)
104 0 : #define NUMAKER_QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos)
105 0 : #define NUMAKER_SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos)
106 0 : #define NUMAKER_SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos)
107 0 : #define NUMAKER_SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos)
108 0 : #define NUMAKER_UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos)
109 0 : #define NUMAKER_UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos)
110 0 : #define NUMAKER_UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos)
111 0 : #define NUMAKER_UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos)
112 0 : #define NUMAKER_UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos)
113 0 : #define NUMAKER_UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos)
114 0 : #define NUMAKER_UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos)
115 0 : #define NUMAKER_UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos)
116 0 : #define NUMAKER_OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos)
117 0 : #define NUMAKER_USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos)
118 0 : #define NUMAKER_EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos)
119 0 : #define NUMAKER_TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos)
120 :
121 0 : #define NUMAKER_SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos)
122 0 : #define NUMAKER_USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos)
123 0 : #define NUMAKER_USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos)
124 0 : #define NUMAKER_WWDT_RST ((8UL<<24) | SYS_IPRST2_WWDTRST_Pos)
125 0 : #define NUMAKER_DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos)
126 0 : #define NUMAKER_EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos)
127 0 : #define NUMAKER_EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos)
128 0 : #define NUMAKER_EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos)
129 0 : #define NUMAKER_EQEI1_RST ((8UL<<24) | SYS_IPRST2_EQEI1RST_Pos)
130 0 : #define NUMAKER_TK_RST ((8UL<<24) | SYS_IPRST2_TKRST_Pos)
131 0 : #define NUMAKER_ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos)
132 0 : #define NUMAKER_ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos)
133 :
134 0 : #define NUMAKER_ACMP2_RST ((0x18UL<<24) | SYS_IPRST3_ACMP2RST_Pos)
135 0 : #define NUMAKER_PWM0_RST ((0x18UL<<24) | SYS_IPRST3_PWM0RST_Pos)
136 0 : #define NUMAKER_PWM1_RST ((0x18UL<<24) | SYS_IPRST3_PWM1RST_Pos)
137 0 : #define NUMAKER_UTCPD0_RST ((0x18UL<<24) | SYS_IPRST3_UTCPD0RST_Pos)
138 :
139 0 : #define NUMAKER_LPPDMA0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPPDMA0RST_Pos)
140 0 : #define NUMAKER_LPGPIO_RST ((0x80UL<<24) | LPSCC_IPRST0_LPGPIORST_Pos)
141 0 : #define NUMAKER_LPSRAM_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSRAMRST_Pos)
142 0 : #define NUMAKER_WDT_RST ((0x80UL<<24) | LPSCC_IPRST0_WDTRST_Pos)
143 0 : #define NUMAKER_LPSPI0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSPI0RST_Pos)
144 0 : #define NUMAKER_LPI2C0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPI2C0RST_Pos)
145 0 : #define NUMAKER_LPUART0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPUART0RST_Pos)
146 0 : #define NUMAKER_LPTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR0RST_Pos)
147 0 : #define NUMAKER_LPTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR1RST_Pos)
148 0 : #define NUMAKER_TTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR0RST_Pos)
149 0 : #define NUMAKER_TTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR1RST_Pos)
150 0 : #define NUMAKER_LPADC0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPADC0RST_Pos)
151 0 : #define NUMAKER_OPA_RST ((0x80UL<<24) | LPSCC_IPRST0_OPARST_Pos)
152 :
153 : /* End of M2L31 BSP sys.h reset module copy */
154 :
155 : #endif
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