Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Nuvoton Technology Corporation.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M333X_RESET_H
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M333X_RESET_H
9 :
10 : /* Beginning of M3331 BSP sys_reg.h reset module copy */
11 :
12 0 : #define SYS_IPRST0_CHIPRST_Pos 0
13 0 : #define SYS_IPRST0_CPURST_Pos 1
14 0 : #define SYS_IPRST0_PDMA0RST_Pos 2
15 0 : #define SYS_IPRST0_EBIRST_Pos 3
16 0 : #define SYS_IPRST0_PDMA1RST_Pos 5
17 0 : #define SYS_IPRST0_SDH0RST_Pos 6
18 0 : #define SYS_IPRST0_CRCRST_Pos 7
19 0 : #define SYS_IPRST0_CANFD0RST_Pos 8
20 0 : #define SYS_IPRST0_CANFD1RST_Pos 9
21 0 : #define SYS_IPRST0_HSUSBDRST_Pos 10
22 0 : #define SYS_IPRST0_PDCIRST_Pos 11
23 0 : #define SYS_IPRST0_HSUSBHRST_Pos 16
24 0 : #define SYS_IPRST1_GPIORST_Pos 1
25 0 : #define SYS_IPRST1_TMR0RST_Pos 2
26 0 : #define SYS_IPRST1_TMR1RST_Pos 3
27 0 : #define SYS_IPRST1_TMR2RST_Pos 4
28 0 : #define SYS_IPRST1_TMR3RST_Pos 5
29 0 : #define SYS_IPRST1_ACMP01RST_Pos 7
30 0 : #define SYS_IPRST1_I2C0RST_Pos 8
31 0 : #define SYS_IPRST1_I2C1RST_Pos 9
32 0 : #define SYS_IPRST1_I2C2RST_Pos 10
33 0 : #define SYS_IPRST1_I3C0RST_Pos 11
34 0 : #define SYS_IPRST1_QSPI0RST_Pos 12
35 0 : #define SYS_IPRST1_SPI0RST_Pos 13
36 0 : #define SYS_IPRST1_SPI1RST_Pos 14
37 0 : #define SYS_IPRST1_SPI2RST_Pos 15
38 0 : #define SYS_IPRST1_UART0RST_Pos 16
39 0 : #define SYS_IPRST1_UART1RST_Pos 17
40 0 : #define SYS_IPRST1_UART2RST_Pos 18
41 0 : #define SYS_IPRST1_UART3RST_Pos 19
42 0 : #define SYS_IPRST1_UART4RST_Pos 20
43 0 : #define SYS_IPRST1_WWDT0RST_Pos 24
44 0 : #define SYS_IPRST1_WWDT1RST_Pos 25
45 0 : #define SYS_IPRST1_EADC0RST_Pos 28
46 0 : #define SYS_IPRST1_I2S0RST_Pos 29
47 0 : #define SYS_IPRST1_HSOTGRST_Pos 30
48 0 : #define SYS_IPRST2_USCI0RST_Pos 8
49 0 : #define SYS_IPRST2_USCI1RST_Pos 9
50 0 : #define SYS_IPRST2_EPWM0RST_Pos 16
51 0 : #define SYS_IPRST2_EPWM1RST_Pos 17
52 0 : #define SYS_IPRST2_BPWM0RST_Pos 18
53 0 : #define SYS_IPRST2_BPWM1RST_Pos 19
54 0 : #define SYS_IPRST2_EQEI0RST_Pos 20
55 0 : #define SYS_IPRST2_ECAP0RST_Pos 26
56 0 : #define SYS_IPRST2_BPWM2RST_Pos 28
57 0 : #define SYS_IPRST2_BPWM3RST_Pos 29
58 0 : #define SYS_IPRST2_BPWM4RST_Pos 30
59 0 : #define SYS_IPRST2_BPWM5RST_Pos 31
60 0 : #define SYS_IPRST3_LLSI0RST_Pos 0
61 0 : #define SYS_IPRST3_LLSI1RST_Pos 1
62 0 : #define SYS_IPRST3_LLSI2RST_Pos 2
63 0 : #define SYS_IPRST3_LLSI3RST_Pos 3
64 0 : #define SYS_IPRST3_LLSI4RST_Pos 4
65 0 : #define SYS_IPRST3_LLSI5RST_Pos 5
66 0 : #define SYS_IPRST3_LLSI6RST_Pos 6
67 0 : #define SYS_IPRST3_LLSI7RST_Pos 7
68 0 : #define SYS_IPRST3_LLSI8RST_Pos 8
69 0 : #define SYS_IPRST3_LLSI9RST_Pos 9
70 0 : #define SYS_IPRST3_ELLSI0RST_Pos 10
71 :
72 : /* End of M3331 BSP sys_reg.h reset module copy */
73 :
74 : /* Beginning of M3331 BSP sys.h reset module copy */
75 :
76 : /*---------------------------------------------------------------------
77 : * Module Reset Control Resister constant definitions.
78 : *---------------------------------------------------------------------
79 : */
80 :
81 0 : #define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos)
82 0 : #define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)
83 0 : #define NUMAKER_PDMA1_RST ((0UL<<24) | SYS_IPRST0_PDMA1RST_Pos)
84 0 : #define NUMAKER_SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos)
85 0 : #define NUMAKER_CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos)
86 0 : #define NUMAKER_CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos)
87 0 : #define NUMAKER_CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos)
88 0 : #define NUMAKER_HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos)
89 0 : #define NUMAKER_HSUSBH_RST ((0UL<<24) | SYS_IPRST0_HSUSBHRST_Pos)
90 0 : #define NUMAKER_PDCI_RST ((0UL<<24) | SYS_IPRST0_PDCIRST_Pos)
91 0 : #define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)
92 0 : #define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)
93 0 : #define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)
94 0 : #define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)
95 0 : #define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)
96 0 : #define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)
97 0 : #define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)
98 0 : #define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)
99 0 : #define NUMAKER_I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos)
100 0 : #define NUMAKER_I3C0_RST ((4UL<<24) | SYS_IPRST1_I3C0RST_Pos)
101 0 : #define NUMAKER_QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos)
102 0 : #define NUMAKER_SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos)
103 0 : #define NUMAKER_SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos)
104 0 : #define NUMAKER_SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos)
105 0 : #define NUMAKER_UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos)
106 0 : #define NUMAKER_UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos)
107 0 : #define NUMAKER_UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos)
108 0 : #define NUMAKER_UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos)
109 0 : #define NUMAKER_UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos)
110 0 : #define NUMAKER_WWDT0_RST ((4UL<<24) | SYS_IPRST1_WWDT0RST_Pos)
111 0 : #define NUMAKER_WWDT1_RST ((4UL<<24) | SYS_IPRST1_WWDT1RST_Pos)
112 0 : #define NUMAKER_EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos)
113 0 : #define NUMAKER_I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos)
114 0 : #define NUMAKER_HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos)
115 0 : #define NUMAKER_USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos)
116 0 : #define NUMAKER_USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos)
117 0 : #define NUMAKER_EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos)
118 0 : #define NUMAKER_EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos)
119 0 : #define NUMAKER_BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos)
120 0 : #define NUMAKER_BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos)
121 0 : #define NUMAKER_EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos)
122 0 : #define NUMAKER_ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos)
123 0 : #define NUMAKER_BPWM2_RST ((8UL<<24) | SYS_IPRST2_BPWM2RST_Pos)
124 0 : #define NUMAKER_BPWM3_RST ((8UL<<24) | SYS_IPRST2_BPWM3RST_Pos)
125 0 : #define NUMAKER_BPWM4_RST ((8UL<<24) | SYS_IPRST2_BPWM4RST_Pos)
126 0 : #define NUMAKER_BPWM5_RST ((8UL<<24) | SYS_IPRST2_BPWM5RST_Pos)
127 0 : #define NUMAKER_LLSI0_RST ((0x18UL<<24) | SYS_IPRST3_LLSI0RST_Pos)
128 0 : #define NUMAKER_LLSI1_RST ((0x18UL<<24) | SYS_IPRST3_LLSI1RST_Pos)
129 0 : #define NUMAKER_LLSI2_RST ((0x18UL<<24) | SYS_IPRST3_LLSI2RST_Pos)
130 0 : #define NUMAKER_LLSI3_RST ((0x18UL<<24) | SYS_IPRST3_LLSI3RST_Pos)
131 0 : #define NUMAKER_LLSI4_RST ((0x18UL<<24) | SYS_IPRST3_LLSI4RST_Pos)
132 0 : #define NUMAKER_LLSI5_RST ((0x18UL<<24) | SYS_IPRST3_LLSI5RST_Pos)
133 0 : #define NUMAKER_LLSI6_RST ((0x18UL<<24) | SYS_IPRST3_LLSI6RST_Pos)
134 0 : #define NUMAKER_LLSI7_RST ((0x18UL<<24) | SYS_IPRST3_LLSI7RST_Pos)
135 0 : #define NUMAKER_LLSI8_RST ((0x18UL<<24) | SYS_IPRST3_LLSI8RST_Pos)
136 0 : #define NUMAKER_LLSI9_RST ((0x18UL<<24) | SYS_IPRST3_LLSI9RST_Pos)
137 0 : #define NUMAKER_ELLSI0_RST ((0x18UL<<24) | SYS_IPRST3_ELLSI0RST_Pos)
138 :
139 : /* End of M3331 BSP sys.h reset module copy */
140 :
141 : #endif
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