Line data Source code
1 0 : /*
2 : * Copyright (c) 2023 Nuvoton Technology Corporation.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
9 :
10 : /* Beginning of M460 BSP sys_reg.h reset module copy */
11 :
12 0 : #define NUMAKER_SYS_IPRST0_PDMA0RST_Pos (2)
13 :
14 0 : #define NUMAKER_SYS_IPRST0_EBIRST_Pos (3)
15 :
16 0 : #define NUMAKER_SYS_IPRST0_EMAC0RST_Pos (5)
17 :
18 0 : #define NUMAKER_SYS_IPRST0_SDH0RST_Pos (6)
19 :
20 0 : #define NUMAKER_SYS_IPRST0_CRCRST_Pos (7)
21 :
22 0 : #define NUMAKER_SYS_IPRST0_CCAPRST_Pos (8)
23 :
24 0 : #define NUMAKER_SYS_IPRST0_HSUSBDRST_Pos (10)
25 :
26 0 : #define NUMAKER_SYS_IPRST0_HBIRST_Pos (11)
27 :
28 0 : #define NUMAKER_SYS_IPRST0_CRPTRST_Pos (12)
29 :
30 0 : #define NUMAKER_SYS_IPRST0_KSRST_Pos (13)
31 :
32 0 : #define NUMAKER_SYS_IPRST0_SPIMRST_Pos (14)
33 :
34 0 : #define NUMAKER_SYS_IPRST0_HSUSBHRST_Pos (16)
35 :
36 0 : #define NUMAKER_SYS_IPRST0_SDH1RST_Pos (17)
37 :
38 0 : #define NUMAKER_SYS_IPRST0_PDMA1RST_Pos (18)
39 :
40 0 : #define NUMAKER_SYS_IPRST0_CANFD0RST_Pos (20)
41 :
42 0 : #define NUMAKER_SYS_IPRST0_CANFD1RST_Pos (21)
43 :
44 0 : #define NUMAKER_SYS_IPRST0_CANFD2RST_Pos (22)
45 :
46 0 : #define NUMAKER_SYS_IPRST0_CANFD3RST_Pos (23)
47 :
48 0 : #define NUMAKER_SYS_IPRST0_BMCRST_Pos (28)
49 :
50 0 : #define NUMAKER_SYS_IPRST1_GPIORST_Pos (1)
51 :
52 0 : #define NUMAKER_SYS_IPRST1_TMR0RST_Pos (2)
53 :
54 0 : #define NUMAKER_SYS_IPRST1_TMR1RST_Pos (3)
55 :
56 0 : #define NUMAKER_SYS_IPRST1_TMR2RST_Pos (4)
57 :
58 0 : #define NUMAKER_SYS_IPRST1_TMR3RST_Pos (5)
59 :
60 0 : #define NUMAKER_SYS_IPRST1_ACMP01RST_Pos (7)
61 :
62 0 : #define NUMAKER_SYS_IPRST1_I2C0RST_Pos (8)
63 :
64 0 : #define NUMAKER_SYS_IPRST1_I2C1RST_Pos (9)
65 :
66 0 : #define NUMAKER_SYS_IPRST1_I2C2RST_Pos (10)
67 :
68 0 : #define NUMAKER_SYS_IPRST1_I2C3RST_Pos (11)
69 :
70 0 : #define NUMAKER_SYS_IPRST1_QSPI0RST_Pos (12)
71 :
72 0 : #define NUMAKER_SYS_IPRST1_SPI0RST_Pos (13)
73 :
74 0 : #define NUMAKER_SYS_IPRST1_SPI1RST_Pos (14)
75 :
76 0 : #define NUMAKER_SYS_IPRST1_SPI2RST_Pos (15)
77 :
78 0 : #define NUMAKER_SYS_IPRST1_UART0RST_Pos (16)
79 :
80 0 : #define NUMAKER_SYS_IPRST1_UART1RST_Pos (17)
81 :
82 0 : #define NUMAKER_SYS_IPRST1_UART2RST_Pos (18)
83 :
84 0 : #define NUMAKER_SYS_IPRST1_UART3RST_Pos (19)
85 :
86 0 : #define NUMAKER_SYS_IPRST1_UART4RST_Pos (20)
87 :
88 0 : #define NUMAKER_SYS_IPRST1_UART5RST_Pos (21)
89 :
90 0 : #define NUMAKER_SYS_IPRST1_UART6RST_Pos (22)
91 :
92 0 : #define NUMAKER_SYS_IPRST1_UART7RST_Pos (23)
93 :
94 0 : #define NUMAKER_SYS_IPRST1_OTGRST_Pos (26)
95 :
96 0 : #define NUMAKER_SYS_IPRST1_USBDRST_Pos (27)
97 :
98 0 : #define NUMAKER_SYS_IPRST1_EADC0RST_Pos (28)
99 :
100 0 : #define NUMAKER_SYS_IPRST1_I2S0RST_Pos (29)
101 :
102 0 : #define NUMAKER_SYS_IPRST1_HSOTGRST_Pos (30)
103 :
104 0 : #define NUMAKER_SYS_IPRST1_TRNGRST_Pos (31)
105 :
106 0 : #define NUMAKER_SYS_IPRST2_SC0RST_Pos (0)
107 :
108 0 : #define NUMAKER_SYS_IPRST2_SC1RST_Pos (1)
109 :
110 0 : #define NUMAKER_SYS_IPRST2_SC2RST_Pos (2)
111 :
112 0 : #define NUMAKER_SYS_IPRST2_I2C4RST_Pos (3)
113 :
114 0 : #define NUMAKER_SYS_IPRST2_QSPI1RST_Pos (4)
115 :
116 0 : #define NUMAKER_SYS_IPRST2_SPI3RST_Pos (6)
117 :
118 0 : #define NUMAKER_SYS_IPRST2_SPI4RST_Pos (7)
119 :
120 0 : #define NUMAKER_SYS_IPRST2_USCI0RST_Pos (8)
121 :
122 0 : #define NUMAKER_SYS_IPRST2_PSIORST_Pos (10)
123 :
124 0 : #define NUMAKER_SYS_IPRST2_DACRST_Pos (12)
125 :
126 0 : #define NUMAKER_SYS_IPRST2_ECAP2RST_Pos (13)
127 :
128 0 : #define NUMAKER_SYS_IPRST2_ECAP3RST_Pos (14)
129 :
130 0 : #define NUMAKER_SYS_IPRST2_EPWM0RST_Pos (16)
131 :
132 0 : #define NUMAKER_SYS_IPRST2_EPWM1RST_Pos (17)
133 :
134 0 : #define NUMAKER_SYS_IPRST2_BPWM0RST_Pos (18)
135 :
136 0 : #define NUMAKER_SYS_IPRST2_BPWM1RST_Pos (19)
137 :
138 0 : #define NUMAKER_SYS_IPRST2_EQEI2RST_Pos (20)
139 :
140 0 : #define NUMAKER_SYS_IPRST2_EQEI3RST_Pos (21)
141 :
142 0 : #define NUMAKER_SYS_IPRST2_EQEI0RST_Pos (22)
143 :
144 0 : #define NUMAKER_SYS_IPRST2_EQEI1RST_Pos (23)
145 :
146 0 : #define NUMAKER_SYS_IPRST2_ECAP0RST_Pos (26)
147 :
148 0 : #define NUMAKER_SYS_IPRST2_ECAP1RST_Pos (27)
149 :
150 0 : #define NUMAKER_SYS_IPRST2_I2S1RST_Pos (29)
151 :
152 0 : #define NUMAKER_SYS_IPRST2_EADC1RST_Pos (31)
153 :
154 0 : #define NUMAKER_SYS_IPRST3_KPIRST_Pos (0)
155 :
156 0 : #define NUMAKER_SYS_IPRST3_EADC2RST_Pos (6)
157 :
158 0 : #define NUMAKER_SYS_IPRST3_ACMP23RST_Pos (7)
159 :
160 0 : #define NUMAKER_SYS_IPRST3_SPI5RST_Pos (8)
161 :
162 0 : #define NUMAKER_SYS_IPRST3_SPI6RST_Pos (9)
163 :
164 0 : #define NUMAKER_SYS_IPRST3_SPI7RST_Pos (10)
165 :
166 0 : #define NUMAKER_SYS_IPRST3_SPI8RST_Pos (11)
167 :
168 0 : #define NUMAKER_SYS_IPRST3_SPI9RST_Pos (12)
169 :
170 0 : #define NUMAKER_SYS_IPRST3_SPI10RST_Pos (13)
171 :
172 0 : #define NUMAKER_SYS_IPRST3_UART8RST_Pos (16)
173 :
174 0 : #define NUMAKER_SYS_IPRST3_UART9RST_Pos (17)
175 :
176 : /* End of M460 BSP sys_reg.h reset module copy */
177 :
178 : /* Beginning of M460 BSP sys.h reset module copy */
179 :
180 : /*---------------------------------------------------------------------
181 : * Module Reset Control Resister constant definitions.
182 : *---------------------------------------------------------------------
183 : */
184 0 : #define NUMAKER_PDMA0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_PDMA0RST_Pos)
185 0 : #define NUMAKER_EBI_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EBIRST_Pos)
186 0 : #define NUMAKER_EMAC0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EMAC0RST_Pos)
187 0 : #define NUMAKER_SDH0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SDH0RST_Pos)
188 0 : #define NUMAKER_CRC_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CRCRST_Pos)
189 0 : #define NUMAKER_CCAP_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CCAPRST_Pos)
190 0 : #define NUMAKER_HSUSBD_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HSUSBDRST_Pos)
191 0 : #define NUMAKER_HBI_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HBIRST_Pos)
192 0 : #define NUMAKER_CRPT_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CRPTRST_Pos)
193 0 : #define NUMAKER_KS_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_KSRST_Pos)
194 0 : #define NUMAKER_SPIM_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SPIMRST_Pos)
195 0 : #define NUMAKER_HSUSBH_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_HSUSBHRST_Pos)
196 0 : #define NUMAKER_SDH1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_SDH1RST_Pos)
197 0 : #define NUMAKER_PDMA1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_PDMA1RST_Pos)
198 0 : #define NUMAKER_CANFD0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD0RST_Pos)
199 0 : #define NUMAKER_CANFD1_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD1RST_Pos)
200 0 : #define NUMAKER_CANFD2_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD2RST_Pos)
201 0 : #define NUMAKER_CANFD3_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_CANFD3RST_Pos)
202 :
203 0 : #define NUMAKER_GPIO_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_GPIORST_Pos)
204 0 : #define NUMAKER_TMR0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR0RST_Pos)
205 0 : #define NUMAKER_TMR1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR1RST_Pos)
206 0 : #define NUMAKER_TMR2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR2RST_Pos)
207 0 : #define NUMAKER_TMR3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TMR3RST_Pos)
208 0 : #define NUMAKER_ACMP01_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_ACMP01RST_Pos)
209 0 : #define NUMAKER_I2C0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C0RST_Pos)
210 0 : #define NUMAKER_I2C1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C1RST_Pos)
211 0 : #define NUMAKER_I2C2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C2RST_Pos)
212 0 : #define NUMAKER_I2C3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2C3RST_Pos)
213 0 : #define NUMAKER_QSPI0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_QSPI0RST_Pos)
214 0 : #define NUMAKER_SPI0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI0RST_Pos)
215 0 : #define NUMAKER_SPI1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI1RST_Pos)
216 0 : #define NUMAKER_SPI2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_SPI2RST_Pos)
217 0 : #define NUMAKER_UART0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART0RST_Pos)
218 0 : #define NUMAKER_UART1_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART1RST_Pos)
219 0 : #define NUMAKER_UART2_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART2RST_Pos)
220 0 : #define NUMAKER_UART3_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART3RST_Pos)
221 0 : #define NUMAKER_UART4_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART4RST_Pos)
222 0 : #define NUMAKER_UART5_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART5RST_Pos)
223 0 : #define NUMAKER_UART6_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART6RST_Pos)
224 0 : #define NUMAKER_UART7_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_UART7RST_Pos)
225 0 : #define NUMAKER_OTG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_OTGRST_Pos)
226 0 : #define NUMAKER_USBD_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_USBDRST_Pos)
227 0 : #define NUMAKER_EADC0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_EADC0RST_Pos)
228 0 : #define NUMAKER_I2S0_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_I2S0RST_Pos)
229 0 : #define NUMAKER_HSOTG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_HSOTGRST_Pos)
230 0 : #define NUMAKER_TRNG_RST ((4UL << 24) | NUMAKER_SYS_IPRST1_TRNGRST_Pos)
231 :
232 0 : #define NUMAKER_SC0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC0RST_Pos)
233 0 : #define NUMAKER_SC1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC1RST_Pos)
234 0 : #define NUMAKER_SC2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SC2RST_Pos)
235 0 : #define NUMAKER_I2C4_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_I2C4RST_Pos)
236 0 : #define NUMAKER_QSPI1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_QSPI1RST_Pos)
237 0 : #define NUMAKER_SPI3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SPI3RST_Pos)
238 0 : #define NUMAKER_SPI4_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_SPI4RST_Pos)
239 0 : #define NUMAKER_USCI0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_USCI0RST_Pos)
240 0 : #define NUMAKER_PSIO_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_PSIORST_Pos)
241 0 : #define NUMAKER_DAC_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_DACRST_Pos)
242 0 : #define NUMAKER_EPWM0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EPWM0RST_Pos)
243 0 : #define NUMAKER_EPWM1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EPWM1RST_Pos)
244 0 : #define NUMAKER_BPWM0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_BPWM0RST_Pos)
245 0 : #define NUMAKER_BPWM1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_BPWM1RST_Pos)
246 0 : #define NUMAKER_EQEI0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI0RST_Pos)
247 0 : #define NUMAKER_EQEI1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI1RST_Pos)
248 0 : #define NUMAKER_EQEI2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI2RST_Pos)
249 0 : #define NUMAKER_EQEI3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EQEI3RST_Pos)
250 0 : #define NUMAKER_ECAP0_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP0RST_Pos)
251 0 : #define NUMAKER_ECAP1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP1RST_Pos)
252 0 : #define NUMAKER_ECAP2_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP2RST_Pos)
253 0 : #define NUMAKER_ECAP3_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_ECAP3RST_Pos)
254 0 : #define NUMAKER_I2S1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_I2S1RST_Pos)
255 0 : #define NUMAKER_EADC1_RST ((8UL << 24) | NUMAKER_SYS_IPRST2_EADC1RST_Pos)
256 :
257 0 : #define NUMAKER_KPI_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_KPIRST_Pos)
258 0 : #define NUMAKER_EADC2_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_EADC2RST_Pos)
259 0 : #define NUMAKER_ACMP23_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_ACMP23RST_Pos)
260 0 : #define NUMAKER_SPI5_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI5RST_Pos)
261 0 : #define NUMAKER_SPI6_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI6RST_Pos)
262 0 : #define NUMAKER_SPI7_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI7RST_Pos)
263 0 : #define NUMAKER_SPI8_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI8RST_Pos)
264 0 : #define NUMAKER_SPI9_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI9RST_Pos)
265 0 : #define NUMAKER_SPI10_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_SPI10RST_Pos)
266 0 : #define NUMAKER_UART8_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_UART8RST_Pos)
267 0 : #define NUMAKER_UART9_RST ((0x18UL << 24) | NUMAKER_SYS_IPRST3_UART9RST_Pos)
268 :
269 : /* End of M460 BSP sys.h reset module copy */
270 :
271 : #endif
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