Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Google Inc
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
       9              : 
      10              : /**
      11              :  * Pack RCC register offset and bit in one 32-bit value.
      12              :  *
      13              :  * 5 LSBs are used to keep bit number in 32-bit RCC register.
      14              :  * Next 12 bits are used to keep RCC register offset.
      15              :  * Remaining bits are unused.
      16              :  *
      17              :  * @param bus STM32 bus name (expands to STM32_RESET_BUS_{bus})
      18              :  * @param bit Reset bit
      19              :  */
      20            1 : #define STM32_RESET(bus, bit) (((STM32_RESET_BUS_##bus) << 5U) | (bit))
      21              : 
      22              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_ */