Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 STMicroelectronics
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
9 :
10 : /**
11 : * Pack RCC register offset and bit in one 32-bit value.
12 : *
13 : * bits[4..0] stores the reset controller bit in 32bit RCC register
14 : * bits[16..5] stores the reset controller set register offset from RCC base
15 : * bits[28..17] stores the reset controller clear register offset from RCC base
16 : *
17 : * @param bus STM32 bus name
18 : * @param bit Reset bit
19 : */
20 1 : #define STM32_RESET(bus, bit) \
21 : (((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
22 :
23 : /* RCC bus reset register offset */
24 0 : #define STM32_RESET_BUS_AHB2_SET 0x6D0
25 0 : #define STM32_RESET_BUS_AHB2_CLR 0x6D4
26 0 : #define STM32_RESET_BUS_AHB4_SET 0x6E0
27 0 : #define STM32_RESET_BUS_AHB4_CLR 0x6E4
28 0 : #define STM32_RESET_BUS_AHB5_SET 0x6E8
29 0 : #define STM32_RESET_BUS_AHB5_CLR 0x6EC
30 0 : #define STM32_RESET_BUS_AHB6_SET 0x6F0
31 0 : #define STM32_RESET_BUS_AHB6_CLR 0x6F4
32 0 : #define STM32_RESET_BUS_APB1_SET 0x6A0
33 0 : #define STM32_RESET_BUS_APB1_CLR 0x6A4
34 0 : #define STM32_RESET_BUS_APB2_SET 0x6A8
35 0 : #define STM32_RESET_BUS_APB2_CLR 0x6AC
36 0 : #define STM32_RESET_BUS_APB3_SET 0x6B0
37 0 : #define STM32_RESET_BUS_APB3_CLR 0x6B4
38 0 : #define STM32_RESET_BUS_APB4_SET 0x6B8
39 0 : #define STM32_RESET_BUS_APB4_CLR 0x6BC
40 0 : #define STM32_RESET_BUS_APB5_SET 0x6C0
41 0 : #define STM32_RESET_BUS_APB5_CLR 0x6C4
42 0 : #define STM32_RESET_BUS_APB6_SET 0x6C8
43 0 : #define STM32_RESET_BUS_APB6_CLR 0x6CC
44 :
45 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_ */
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