Line data    Source code

       1            0 : /*
       2              :  * Copyright (C) 2025 Savoir-faire Linux, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP2_RESET_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP2_RESET_H_
       9              : 
      10              : /**
      11              :  * Pack RCC register offset and bit in one 32-bit value.
      12              :  *
      13              :  * 5 LSBs are used to keep bit number in 32-bit RCC register.
      14              :  * Next 12 bits are used to keep RCC register offset.
      15              :  * Remaining bits are unused.
      16              :  *
      17              :  * @param per STM32 peripheral name
      18              :  * @param bit Reset bit
      19              :  */
      20            1 : #define STM32_RESET(per, bit) (((STM32_RESET_PERIPH_##per##) << 5U) | (bit))
      21              : 
      22              : /* Reset reg */
      23            0 : #define STM32_RST       0U
      24              : 
      25              : /* USART/UART Peripheral */
      26            0 : #define STM32_RESET_PERIPH_USART1       0x77C
      27            0 : #define STM32_RESET_PERIPH_USART2       0x780
      28            0 : #define STM32_RESET_PERIPH_USART3       0x784
      29            0 : #define STM32_RESET_PERIPH_UART4        0x788
      30            0 : #define STM32_RESET_PERIPH_UART5        0x78C
      31            0 : #define STM32_RESET_PERIPH_USART6       0x790
      32            0 : #define STM32_RESET_PERIPH_UART7        0x794
      33            0 : #define STM32_RESET_PERIPH_UART8        0x798
      34            0 : #define STM32_RESET_PERIPH_UART9        0x79C
      35              : 
      36              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP2_RESET_H_ */