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1 0 : /* 2 : * Copyright 2023 NXP 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : /* Logic Trigger Numbers. See Trgmux_Ip_Init_PBcfg.h */ 8 0 : #define TRGMUX_LOGIC_GROUP_0_TRIGGER_0 (0) /* Logic Trigger 0 */ 9 0 : #define TRGMUX_LOGIC_GROUP_0_TRIGGER_1 (1) /* Logic Trigger 1 */ 10 0 : #define TRGMUX_LOGIC_GROUP_1_TRIGGER_0 (2) /* Logic Trigger 2 */ 11 0 : #define TRGMUX_LOGIC_GROUP_1_TRIGGER_1 (3) /* Logic Trigger 3 */ 12 : 13 : /*----------------------------------------------- 14 : * TRGMUX HARDWARE TRIGGER INPUT 15 : * See Trgmux_Ip_Cfg_Defines.h 16 : *----------------------------------------------- 17 : */ 18 0 : #define TRGMUX_IP_INPUT_SIUL2_IN0 (60) 19 0 : #define TRGMUX_IP_INPUT_SIUL2_IN1 (61) 20 0 : #define TRGMUX_IP_INPUT_SIUL2_IN2 (62) 21 0 : #define TRGMUX_IP_INPUT_SIUL2_IN3 (63) 22 0 : #define TRGMUX_IP_INPUT_SIUL2_IN4 (64) 23 0 : #define TRGMUX_IP_INPUT_SIUL2_IN5 (65) 24 0 : #define TRGMUX_IP_INPUT_SIUL2_IN6 (66) 25 0 : #define TRGMUX_IP_INPUT_SIUL2_IN7 (67) 26 0 : #define TRGMUX_IP_INPUT_SIUL2_IN8 (68) 27 0 : #define TRGMUX_IP_INPUT_SIUL2_IN9 (69) 28 0 : #define TRGMUX_IP_INPUT_SIUL2_IN10 (70) 29 0 : #define TRGMUX_IP_INPUT_SIUL2_IN11 (71) 30 0 : #define TRGMUX_IP_INPUT_SIUL2_IN12 (72) 31 0 : #define TRGMUX_IP_INPUT_SIUL2_IN13 (73) 32 0 : #define TRGMUX_IP_INPUT_SIUL2_IN14 (74) 33 0 : #define TRGMUX_IP_INPUT_SIUL2_IN15 (75) 34 : 35 0 : #define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I0 (105) 36 0 : #define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I1 (106) 37 0 : #define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2 (107) 38 0 : #define TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3 (108) 39 : 40 : /*----------------------------------------------- 41 : * TRGMUX HARDWARE TRIGGER OUTPUT 42 : * See Trgmux_Ip_Cfg_Defines.h 43 : *----------------------------------------------- 44 : */ 45 0 : #define TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 (144) 46 0 : #define TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 (145) 47 0 : #define TRGMUX_IP_OUTPUT_LCU1_0_INP_I2 (146) 48 0 : #define TRGMUX_IP_OUTPUT_LCU1_0_INP_I3 (147) 49 : 50 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH1 (32) 51 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH2 (33) 52 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH3 (34) 53 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH1_4_IPP_IND_CH4 (35) 54 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH5 (36) 55 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 (37) 56 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 (38) 57 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH9 (39) 58 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH10 (40) 59 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH11 (41) 60 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH12 (42) 61 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH10_13_IPP_IND_CH13 (43) 62 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH14 (44) 63 0 : #define TRGMUX_IP_OUTPUT_EMIOS0_CH14_15_IPP_IND_CH15 (45) 64 : 65 : /*----------------------------------------------- 66 : * LCU SOURCE MUX SELECT 67 : * See Lcu_Ip_Cfg_Defines.h 68 : *----------------------------------------------- 69 : */ 70 0 : #define LCU_IP_MUX_SEL_LOGIC_0 (0) 71 0 : #define LCU_IP_MUX_SEL_LU_IN_0 (1) 72 0 : #define LCU_IP_MUX_SEL_LU_IN_1 (2) 73 0 : #define LCU_IP_MUX_SEL_LU_IN_2 (3) 74 0 : #define LCU_IP_MUX_SEL_LU_IN_3 (4) 75 0 : #define LCU_IP_MUX_SEL_LU_IN_4 (5) 76 0 : #define LCU_IP_MUX_SEL_LU_IN_5 (6) 77 0 : #define LCU_IP_MUX_SEL_LU_IN_6 (7) 78 0 : #define LCU_IP_MUX_SEL_LU_IN_7 (8) 79 0 : #define LCU_IP_MUX_SEL_LU_IN_8 (9) 80 0 : #define LCU_IP_MUX_SEL_LU_IN_9 (10) 81 0 : #define LCU_IP_MUX_SEL_LU_IN_10 (11) 82 0 : #define LCU_IP_MUX_SEL_LU_IN_11 (12) 83 0 : #define LCU_IP_MUX_SEL_LU_OUT_0 (13) 84 0 : #define LCU_IP_MUX_SEL_LU_OUT_1 (14) 85 0 : #define LCU_IP_MUX_SEL_LU_OUT_2 (15) 86 0 : #define LCU_IP_MUX_SEL_LU_OUT_3 (16) 87 0 : #define LCU_IP_MUX_SEL_LU_OUT_4 (17) 88 0 : #define LCU_IP_MUX_SEL_LU_OUT_5 (18) 89 0 : #define LCU_IP_MUX_SEL_LU_OUT_6 (19) 90 0 : #define LCU_IP_MUX_SEL_LU_OUT_7 (20) 91 0 : #define LCU_IP_MUX_SEL_LU_OUT_8 (21) 92 0 : #define LCU_IP_MUX_SEL_LU_OUT_9 (22) 93 0 : #define LCU_IP_MUX_SEL_LU_OUT_10 (23) 94 0 : #define LCU_IP_MUX_SEL_LU_OUT_11 (24) 95 : 96 0 : #define LCU_IP_IN_0 (0) 97 0 : #define LCU_IP_IN_1 (1) 98 0 : #define LCU_IP_IN_2 (2) 99 0 : #define LCU_IP_IN_3 (3) 100 0 : #define LCU_IP_IN_4 (4) 101 0 : #define LCU_IP_IN_5 (5) 102 0 : #define LCU_IP_IN_6 (6) 103 0 : #define LCU_IP_IN_7 (7) 104 0 : #define LCU_IP_IN_8 (8) 105 0 : #define LCU_IP_IN_9 (9) 106 0 : #define LCU_IP_IN_10 (10) 107 0 : #define LCU_IP_IN_11 (11)
