Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2021 Intel Corporation
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
       8              : 
       9              : /**
      10              :  * @addtogroup spi_interface
      11              :  * @{
      12              :  */
      13              : 
      14              : /**
      15              :  * @name SPI duplex mode
      16              :  * @{
      17              :  *
      18              :  * Some controllers support half duplex transfer, which results in 3-wire usage.
      19              :  * By default, full duplex will prevail.
      20              :  */
      21            0 : #define SPI_FULL_DUPLEX         (0U << 11)
      22            0 : #define SPI_HALF_DUPLEX         (1U << 11)
      23              : /** @} */
      24              : 
      25              : /**
      26              :  * @name SPI Frame Format
      27              :  * @{
      28              :  *
      29              :  * 2 frame formats are exposed: Motorola and TI.
      30              :  * The main difference is the behavior of the CS line. In Motorola it stays
      31              :  * active the whole transfer. In TI, it's active only one serial clock period
      32              :  * prior to actually make the transfer, it is thus inactive during the transfer,
      33              :  * which ends when the clocks ends as well.
      34              :  * By default, as it is the most commonly used, the Motorola frame format
      35              :  * will prevail.
      36              :  */
      37            0 : #define SPI_FRAME_FORMAT_MOTOROLA       (0U << 15)
      38            0 : #define SPI_FRAME_FORMAT_TI             (1U << 15)
      39              : /** @} */
      40              : 
      41              : /**
      42              :  * @}
      43              :  */
      44              : 
      45              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_ */