Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2021 Intel Corporation
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_
       8              : 
       9              : /**
      10              :  * @brief SPI Interface
      11              :  * @defgroup spi_interface SPI Interface
      12              :  * @ingroup io_interfaces
      13              :  * @{
      14              :  */
      15              : 
      16              : /**
      17              :  * @name SPI duplex mode
      18              :  * @{
      19              :  *
      20              :  * Some controllers support half duplex transfer, which results in 3-wire usage.
      21              :  * By default, full duplex will prevail.
      22              :  */
      23            0 : #define SPI_FULL_DUPLEX         (0U << 11)
      24            0 : #define SPI_HALF_DUPLEX         (1U << 11)
      25              : /** @} */
      26              : 
      27              : /**
      28              :  * @name SPI Frame Format
      29              :  * @{
      30              :  *
      31              :  * 2 frame formats are exposed: Motorola and TI.
      32              :  * The main difference is the behavior of the CS line. In Motorola it stays
      33              :  * active the whole transfer. In TI, it's active only one serial clock period
      34              :  * prior to actually make the transfer, it is thus inactive during the transfer,
      35              :  * which ends when the clocks ends as well.
      36              :  * By default, as it is the most commonly used, the Motorola frame format
      37              :  * will prevail.
      38              :  */
      39            0 : #define SPI_FRAME_FORMAT_MOTOROLA       (0U << 15)
      40            0 : #define SPI_FRAME_FORMAT_TI             (1U << 15)
      41              : /** @} */
      42              : 
      43              : /**
      44              :  * @}
      45              :  */
      46              : 
      47              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SPI_SPI_H_ */