Line data Source code
1 1 : /*
2 : * Copyright 2023 NXP
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : /**
8 : * @file
9 : * @brief Definitions for IEEE 802.3 management interface
10 : */
11 :
12 : #ifndef ZEPHYR_INCLUDE_NET_MDIO_H_
13 : #define ZEPHYR_INCLUDE_NET_MDIO_H_
14 :
15 : /**
16 : * @brief Definitions for IEEE 802.3 management interface
17 : * @defgroup ethernet_mdio IEEE 802.3 management interface
18 : * @since 3.5
19 : * @version 0.8.0
20 : * @ingroup ethernet
21 : * @{
22 : */
23 :
24 : #ifdef __cplusplus
25 : extern "C" {
26 : #endif
27 :
28 : /** MDIO transaction operation code */
29 1 : enum mdio_opcode {
30 : /** IEEE 802.3 22.2.4.5.4 write operation */
31 : MDIO_OP_C22_WRITE = 1,
32 :
33 : /** IEEE 802.3 22.2.4.5.4 read operation */
34 : MDIO_OP_C22_READ = 2,
35 :
36 : /** IEEE 802.3 45.3.4 address operation */
37 : MDIO_OP_C45_ADDRESS = 0,
38 :
39 : /** IEEE 802.3 45.3.4 write operation */
40 : MDIO_OP_C45_WRITE = 1,
41 :
42 : /** IEEE 802.3 45.3.4 post-read-increment-address operation */
43 : MDIO_OP_C45_READ_INC = 2,
44 :
45 : /** IEEE 802.3 45.3.4 read operation */
46 : MDIO_OP_C45_READ = 3
47 : };
48 :
49 : /* MDIO Manageable Device addresses */
50 : /** Physical Medium Attachment / Physical Medium Dependent */
51 1 : #define MDIO_MMD_PMAPMD 0x01U
52 : /** WAN Interface Sublayer */
53 1 : #define MDIO_MMD_WIS 0x02U
54 : /** Physical Coding Sublayer */
55 1 : #define MDIO_MMD_PCS 0x03U
56 : /** PHY Extender Sublayer */
57 1 : #define MDIO_MMD_PHYXS 0x04U
58 : /** DTE Extender Sublayer */
59 1 : #define MDIO_MMD_DTEXS 0x05U
60 : /** Transmission Convergence */
61 1 : #define MDIO_MMD_TC 0x06U
62 : /** Auto-negotiation */
63 1 : #define MDIO_MMD_AN 0x07U
64 : /** Separated PMA (1) */
65 1 : #define MDIO_MMD_SEPARATED_PMA1 0x08U
66 : /** Separated PMA (2) */
67 1 : #define MDIO_MMD_SEPARATED_PMA2 0x09U
68 : /** Separated PMA (3) */
69 1 : #define MDIO_MMD_SEPARATED_PMA3 0x0AU
70 : /** Separated PMA (4) */
71 1 : #define MDIO_MMD_SEPARATED_PMA4 0x0BU
72 : /** Clause 22 extension */
73 1 : #define MDIO_MMD_C22EXT 0x1DU
74 : /** Vendor Specific 1 */
75 1 : #define MDIO_MMD_VENDOR_SPECIFIC1 0x1EU
76 : /** Vendor Specific 2 */
77 1 : #define MDIO_MMD_VENDOR_SPECIFIC2 0x1FU
78 :
79 : /* MDIO generic registers */
80 : /** Control 1 */
81 1 : #define MDIO_CTRL1 0x0000U
82 : /** Status 1 */
83 1 : #define MDIO_STAT1 0x0001U
84 : /** Device identifier (1) */
85 1 : #define MDIO_DEVID1 0x0002U
86 : /** Device identifier (2) */
87 1 : #define MDIO_DEVID2 0x0003U
88 : /** Speed ability */
89 1 : #define MDIO_SPEED 0x0004U
90 : /** Devices in package (1) */
91 1 : #define MDIO_DEVS1 0x0005U
92 : /** Devices in package (2) */
93 1 : #define MDIO_DEVS2 0x0006U
94 : /** Control 2 */
95 1 : #define MDIO_CTRL2 0x0007U
96 : /** Status 2 */
97 1 : #define MDIO_STAT2 0x0008U
98 : /** Package identifier (1) */
99 1 : #define MDIO_PKGID1 0x000EU
100 : /** Package identifier (2) */
101 1 : #define MDIO_PKGID2 0x000FU
102 : /* PCS Register: EEE capability Register */
103 0 : #define MDIO_PCS_EEE_CAP 0x0014U
104 : /* Auto-negotiation Register: EEE advertisement Register */
105 0 : #define MDIO_AN_EEE_ADV 0x003CU
106 :
107 :
108 : /* BASE-T1 registers */
109 : /** BASE-T1 Auto-negotiation control */
110 1 : #define MDIO_AN_T1_CTRL 0x0200U
111 : /** BASE-T1 Auto-negotiation status */
112 1 : #define MDIO_AN_T1_STAT 0x0201U
113 : /** BASE-T1 Auto-negotiation advertisement register [15:0] */
114 1 : #define MDIO_AN_T1_ADV_L 0x0202U
115 : /** BASE-T1 Auto-negotiation advertisement register [31:16] */
116 1 : #define MDIO_AN_T1_ADV_M 0x0203U
117 : /** BASE-T1 Auto-negotiation advertisement register [47:32] */
118 1 : #define MDIO_AN_T1_ADV_H 0x0204U
119 : /** BASE-T1 PMA/PMD control register */
120 1 : #define MDIO_PMA_PMD_BT1_CTRL 0x0834U
121 :
122 : /* BASE-T1 Auto-negotiation Control register */
123 : /** Auto-negotiation Restart */
124 1 : #define MDIO_AN_T1_CTRL_RESTART BIT(9)
125 : /** Auto-negotiation Enable */
126 1 : #define MDIO_AN_T1_CTRL_EN BIT(12)
127 :
128 : /* BASE-T1 Auto-negotiation Status register */
129 : /** Link Status */
130 1 : #define MDIO_AN_T1_STAT_LINK_STATUS BIT(2)
131 : /** Auto-negotiation Ability */
132 1 : #define MDIO_AN_T1_STAT_ABLE BIT(3)
133 : /** Auto-negotiation Remote Fault */
134 1 : #define MDIO_AN_T1_STAT_REMOTE_FAULT BIT(4)
135 : /** Auto-negotiation Complete */
136 1 : #define MDIO_AN_T1_STAT_COMPLETE BIT(5)
137 : /** Page Received */
138 1 : #define MDIO_AN_T1_STAT_PAGE_RX BIT(6)
139 :
140 : /* BASE-T1 Auto-negotiation Advertisement register [15:0] */
141 : /** Pause Ability */
142 1 : #define MDIO_AN_T1_ADV_L_PAUSE_CAP BIT(10)
143 : /** Pause Ability */
144 1 : #define MDIO_AN_T1_ADV_L_PAUSE_ASYM BIT(11)
145 : /** Force Master/Slave Configuration */
146 1 : #define MDIO_AN_T1_ADV_L_FORCE_MS BIT(12)
147 : /** Remote Fault */
148 1 : #define MDIO_AN_T1_ADV_L_REMOTE_FAULT BIT(13)
149 : /** Acknowledge (ACK) */
150 1 : #define MDIO_AN_T1_ADV_L_ACK BIT(14)
151 : /** Next Page Request */
152 1 : #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ BIT(15)
153 :
154 : /* BASE-T1 Auto-negotiation Advertisement register [31:16] */
155 : /** 10BASE-T1L Ability */
156 1 : #define MDIO_AN_T1_ADV_M_B10L BIT(14)
157 : /** Master/slave Configuration */
158 1 : #define MDIO_AN_T1_ADV_M_MST BIT(4)
159 :
160 : /* BASE-T1 Auto-negotiation Advertisement register [47:32] */
161 : /** 10BASE-T1L High Level Transmit Operating Mode Request */
162 1 : #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ BIT(12)
163 : /** 10BASE-T1L High Level Transmit Operating Mode Ability */
164 1 : #define MDIO_AN_T1_ADV_H_10L_TX_HI BIT(13)
165 :
166 : /* BASE-T1 PMA/PMD control register */
167 : /** BASE-T1 master/slave configuration */
168 1 : #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST BIT(14)
169 :
170 :
171 : /* 10BASE-T1L registers */
172 : /** 10BASE-T1L PMA control */
173 1 : #define MDIO_PMA_B10L_CTRL 0x08F6U
174 : /** 10BASE-T1L PMA status */
175 1 : #define MDIO_PMA_B10L_STAT 0x08F7U
176 : /** 10BASE-T1L PMA link status*/
177 1 : #define MDIO_PMA_B10L_LINK_STAT 0x8302U
178 : /** 10BASE-T1L PCS control */
179 1 : #define MDIO_PCS_B10L_CTRL 0x08E6U
180 : /** 10BASE-T1L PCS status */
181 1 : #define MDIO_PCS_B10L_STAT 0x08E7U
182 :
183 : /* 10BASE-T1L PMA control register */
184 : /** 10BASE-T1L Transmit Disable Mode */
185 1 : #define MDIO_PMA_B10L_CTRL_TX_DIS_MODE_EN BIT(14)
186 : /** 10BASE-T1L Transmit Voltage Amplitude Control */
187 1 : #define MDIO_PMA_B10L_CTRL_TX_LVL_HI BIT(12)
188 : /** 10BASE-T1L EEE Enable */
189 1 : #define MDIO_PMA_B10L_CTRL_EEE BIT(10)
190 : /** 10BASE-T1L PMA Loopback */
191 1 : #define MDIO_PMA_B10L_CTRL_LB_PMA_LOC_EN BIT(0)
192 :
193 : /* 10BASE-T1L PMA status register */
194 : /** 10BASE-T1L PMA receive link up */
195 1 : #define MDIO_PMA_B10L_STAT_LINK BIT(0)
196 : /** 10BASE-T1L Fault condition detected */
197 1 : #define MDIO_PMA_B10L_STAT_FAULT BIT(1)
198 : /** 10BASE-T1L Receive polarity is reversed */
199 1 : #define MDIO_PMA_B10L_STAT_POLARITY BIT(2)
200 : /** 10BASE-T1L Able to detect fault on receive path */
201 1 : #define MDIO_PMA_B10L_STAT_RECV_FAULT BIT(9)
202 : /** 10BASE-T1L PHY has EEE ability */
203 1 : #define MDIO_PMA_B10L_STAT_EEE BIT(10)
204 : /** 10BASE-T1L PMA has low-power ability */
205 1 : #define MDIO_PMA_B10L_STAT_LOW_POWER BIT(11)
206 : /** 10BASE-T1L PHY has 2.4 Vpp operating mode ability */
207 1 : #define MDIO_PMA_B10L_STAT_2V4_ABLE BIT(12)
208 : /** 10BASE-T1L PHY has loopback ability */
209 1 : #define MDIO_PMA_B10L_STAT_LB_ABLE BIT(13)
210 :
211 : /* 10BASE-T1L PMA link status*/
212 : /** 10BASE-T1L Remote Receiver Status OK Latch Low */
213 1 : #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK_LL BIT(9)
214 : /** 10BASE-T1L Remote Receiver Status OK */
215 1 : #define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK BIT(8)
216 : /** 10BASE-T1L Local Receiver Status OK */
217 1 : #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK_LL BIT(7)
218 : /** 10BASE-T1L Local Receiver Status OK */
219 1 : #define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK BIT(6)
220 : /** 10BASE-T1L Descrambler Status OK Latch Low */
221 1 : #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK_LL BIT(5)
222 : /** 10BASE-T1L Descrambler Status OK */
223 1 : #define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK BIT(4)
224 : /** 10BASE-T1L Link Status OK Latch Low */
225 1 : #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK_LL BIT(1)
226 : /** 10BASE-T1L Link Status OK */
227 1 : #define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK BIT(0)
228 :
229 : /* 10BASE-T1L PCS control */
230 : /** 10BASE-T1L PCS Loopback Enable */
231 1 : #define MDIO_PCS_B10L_CTRL_LB_PCS_EN BIT(14)
232 :
233 : /* 10BASE-T1L PCS status */
234 : /** 10BASE-T1L PCS Descrambler Status */
235 1 : #define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL BIT(2)
236 :
237 : /* Auto-negotiation Register: EEE advertisement Register */
238 : /** Advertise 1000T capability */
239 1 : #define MDIO_AN_EEE_ADV_1000T BIT(2)
240 : /** Advertise 100TX capability */
241 1 : #define MDIO_AN_EEE_ADV_100TX BIT(1)
242 :
243 : #ifdef __cplusplus
244 : }
245 : #endif
246 :
247 : /**
248 : * @}
249 : */
250 :
251 : #endif /* ZEPHYR_INCLUDE_NET_MDIO_H_ */
|
