Line data Source code
1 1 : /*
2 : * Copyright (c) 2016 Piotr Mienkowski
3 : * Copyright 2022 NXP
4 : *
5 : * SPDX-License-Identifier: Apache-2.0
6 : */
7 :
8 : /** @file
9 : * @brief Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers
10 : */
11 :
12 : #ifndef ZEPHYR_INCLUDE_NET_MII_H_
13 : #define ZEPHYR_INCLUDE_NET_MII_H_
14 :
15 : #include <zephyr/sys/util_macro.h>
16 :
17 : /**
18 : * @brief Ethernet MII (media independent interface) functions
19 : * @defgroup ethernet_mii Ethernet MII Support Functions
20 : * @since 1.7
21 : * @version 0.8.0
22 : * @ingroup ethernet
23 : * @{
24 : */
25 :
26 : /* MII management registers */
27 : /** Basic Mode Control Register */
28 1 : #define MII_BMCR 0x0
29 : /** Basic Mode Status Register */
30 1 : #define MII_BMSR 0x1
31 : /** PHY ID 1 Register */
32 1 : #define MII_PHYID1R 0x2
33 : /** PHY ID 2 Register */
34 1 : #define MII_PHYID2R 0x3
35 : /** Auto-Negotiation Advertisement Register */
36 1 : #define MII_ANAR 0x4
37 : /** Auto-Negotiation Link Partner Ability Reg */
38 1 : #define MII_ANLPAR 0x5
39 : /** Auto-Negotiation Expansion Register */
40 1 : #define MII_ANER 0x6
41 : /** Auto-Negotiation Next Page Transmit Register */
42 1 : #define MII_ANNPTR 0x7
43 : /** Auto-Negotiation Link Partner Received Next Page Reg */
44 1 : #define MII_ANLPRNPR 0x8
45 : /** 1000BASE-T Control Register */
46 1 : #define MII_1KTCR 0x9
47 : /** 1000BASE-T Status Register */
48 1 : #define MII_1KSTSR 0xa
49 : /** MMD Access Control Register */
50 1 : #define MII_MMD_ACR 0xd
51 : /** MMD Access Address Data Register */
52 1 : #define MII_MMD_AADR 0xe
53 : /** Extended Status Register */
54 1 : #define MII_ESTAT 0xf
55 :
56 : /* Basic Mode Control Register (BMCR) bit definitions */
57 0 : #define MII_BMCR_RESET_BIT 15
58 0 : #define MII_BMCR_LOOPBACK_BIT 14
59 0 : #define MII_BMCR_SPEED_LSB_BIT 13
60 0 : #define MII_BMCR_AUTONEG_ENABLE_BIT 12
61 0 : #define MII_BMCR_POWER_DOWN_BIT 11
62 0 : #define MII_BMCR_ISOLATE_BIT 10
63 0 : #define MII_BMCR_AUTONEG_RESTART_BIT 9
64 0 : #define MII_BMCR_DUPLEX_MODE_BIT 8
65 0 : #define MII_BMCR_SPEED_MSB_BIT 6
66 : /** PHY reset */
67 1 : #define MII_BMCR_RESET BIT(MII_BMCR_RESET_BIT)
68 : /** enable loopback mode */
69 1 : #define MII_BMCR_LOOPBACK BIT(MII_BMCR_LOOPBACK_BIT)
70 : /** 10=1000Mbps 01=100Mbps; 00=10Mbps */
71 1 : #define MII_BMCR_SPEED_LSB BIT(MII_BMCR_SPEED_LSB_BIT)
72 : /** Auto-Negotiation enable */
73 1 : #define MII_BMCR_AUTONEG_ENABLE BIT(MII_BMCR_AUTONEG_ENABLE_BIT)
74 : /** power down mode */
75 1 : #define MII_BMCR_POWER_DOWN BIT(MII_BMCR_POWER_DOWN_BIT)
76 : /** isolate electrically PHY from MII */
77 1 : #define MII_BMCR_ISOLATE BIT(MII_BMCR_ISOLATE_BIT)
78 : /** restart auto-negotiation */
79 1 : #define MII_BMCR_AUTONEG_RESTART BIT(MII_BMCR_AUTONEG_RESTART_BIT)
80 : /** full duplex mode */
81 1 : #define MII_BMCR_DUPLEX_MODE BIT(MII_BMCR_DUPLEX_MODE_BIT)
82 : /** 10=1000Mbps 01=100Mbps; 00=10Mbps */
83 1 : #define MII_BMCR_SPEED_MSB BIT(MII_BMCR_SPEED_MSB_BIT)
84 : /** Link Speed Field */
85 1 : #define MII_BMCR_SPEED_MASK (MII_BMCR_SPEED_MSB | MII_BMCR_SPEED_LSB)
86 : /** select speed 10 Mb/s */
87 1 : #define MII_BMCR_SPEED_10 0
88 : /** select speed 100 Mb/s */
89 1 : #define MII_BMCR_SPEED_100 BIT(MII_BMCR_SPEED_LSB_BIT)
90 : /** select speed 1000 Mb/s */
91 1 : #define MII_BMCR_SPEED_1000 BIT(MII_BMCR_SPEED_MSB_BIT)
92 :
93 : /* Basic Mode Status Register (BMSR) bit definitions */
94 : /** 100BASE-T4 capable */
95 1 : #define MII_BMSR_100BASE_T4 BIT(15)
96 : /** 100BASE-X full duplex capable */
97 1 : #define MII_BMSR_100BASE_X_FULL BIT(14)
98 : /** 100BASE-X half duplex capable */
99 1 : #define MII_BMSR_100BASE_X_HALF BIT(13)
100 : /** 10 Mb/s full duplex capable */
101 1 : #define MII_BMSR_10_FULL BIT(12)
102 : /** 10 Mb/s half duplex capable */
103 1 : #define MII_BMSR_10_HALF BIT(11)
104 : /** 100BASE-T2 full duplex capable */
105 1 : #define MII_BMSR_100BASE_T2_FULL BIT(10)
106 : /** 100BASE-T2 half duplex capable */
107 1 : #define MII_BMSR_100BASE_T2_HALF BIT(9)
108 : /** extend status information in reg 15 */
109 1 : #define MII_BMSR_EXTEND_STATUS BIT(8)
110 : /** PHY accepts management frames with preamble suppressed */
111 1 : #define MII_BMSR_MF_PREAMB_SUPPR BIT(6)
112 : /** Auto-negotiation process completed */
113 1 : #define MII_BMSR_AUTONEG_COMPLETE BIT(5)
114 : /** remote fault detected */
115 1 : #define MII_BMSR_REMOTE_FAULT BIT(4)
116 : /** PHY is able to perform Auto-Negotiation */
117 1 : #define MII_BMSR_AUTONEG_ABILITY BIT(3)
118 : /** link is up */
119 1 : #define MII_BMSR_LINK_STATUS BIT(2)
120 : /** jabber condition detected */
121 1 : #define MII_BMSR_JABBER_DETECT BIT(1)
122 : /** extended register capabilities */
123 1 : #define MII_BMSR_EXTEND_CAPAB BIT(0)
124 :
125 : /* Auto-negotiation Advertisement Register (ANAR) bit definitions */
126 : /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
127 0 : #define MII_ADVERTISE_NEXT_PAGE_BIT 15
128 0 : #define MII_ADVERTISE_LPACK_BIT 14
129 0 : #define MII_ADVERTISE_REMOTE_FAULT_BIT 13
130 0 : #define MII_ADVERTISE_ASYM_PAUSE_BIT 11
131 0 : #define MII_ADVERTISE_PAUSE_BIT 10
132 0 : #define MII_ADVERTISE_100BASE_T4_BIT 9
133 0 : #define MII_ADVERTISE_100_FULL_BIT 8
134 0 : #define MII_ADVERTISE_100_HALF_BIT 7
135 0 : #define MII_ADVERTISE_10_FULL_BIT 6
136 0 : #define MII_ADVERTISE_10_HALF_BIT 5
137 : /** next page */
138 1 : #define MII_ADVERTISE_NEXT_PAGE BIT(MII_ADVERTISE_NEXT_PAGE_BIT)
139 : /** link partner acknowledge response */
140 1 : #define MII_ADVERTISE_LPACK BIT(MII_ADVERTISE_LPACK_BIT)
141 : /** remote fault */
142 1 : #define MII_ADVERTISE_REMOTE_FAULT BIT(MII_ADVERTISE_REMOTE_FAULT_BIT)
143 : /** try for asymmetric pause */
144 1 : #define MII_ADVERTISE_ASYM_PAUSE BIT(MII_ADVERTISE_ASYM_PAUSE_BIT)
145 : /** try for pause */
146 1 : #define MII_ADVERTISE_PAUSE BIT(MII_ADVERTISE_PAUSE_BIT)
147 : /** try for 100BASE-T4 support */
148 1 : #define MII_ADVERTISE_100BASE_T4 BIT(MII_ADVERTISE_100BASE_T4_BIT)
149 : /** try for 100BASE-X full duplex support */
150 1 : #define MII_ADVERTISE_100_FULL BIT(MII_ADVERTISE_100_FULL_BIT)
151 : /** try for 100BASE-X support */
152 1 : #define MII_ADVERTISE_100_HALF BIT(MII_ADVERTISE_100_HALF_BIT)
153 : /** try for 10 Mb/s full duplex support */
154 1 : #define MII_ADVERTISE_10_FULL BIT(MII_ADVERTISE_10_FULL_BIT)
155 : /** try for 10 Mb/s half duplex support */
156 1 : #define MII_ADVERTISE_10_HALF BIT(MII_ADVERTISE_10_HALF_BIT)
157 : /** Selector Field Mask */
158 1 : #define MII_ADVERTISE_SEL_MASK (0x1F << 0)
159 : /** Selector Field */
160 1 : #define MII_ADVERTISE_SEL_IEEE_802_3 0x01
161 :
162 : /* 1000BASE-T Control Register bit definitions */
163 0 : #define MII_ADVERTISE_1000_FULL_BIT 9
164 0 : #define MII_ADVERTISE_1000_HALF_BIT 8
165 : /** try for 1000BASE-T full duplex support */
166 1 : #define MII_ADVERTISE_1000_FULL BIT(MII_ADVERTISE_1000_FULL_BIT)
167 : /** try for 1000BASE-T half duplex support */
168 1 : #define MII_ADVERTISE_1000_HALF BIT(MII_ADVERTISE_1000_HALF_BIT)
169 :
170 : /** Advertise all speeds */
171 1 : #define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
172 : MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
173 : MII_ADVERTISE_SEL_IEEE_802_3)
174 :
175 : /* Extended Status Register bit definitions */
176 : /** 1000BASE-X full-duplex capable */
177 1 : #define MII_ESTAT_1000BASE_X_FULL BIT(15)
178 : /** 1000BASE-X half-duplex capable */
179 1 : #define MII_ESTAT_1000BASE_X_HALF BIT(14)
180 : /** 1000BASE-T full-duplex capable */
181 1 : #define MII_ESTAT_1000BASE_T_FULL BIT(13)
182 : /** 1000BASE-T half-duplex capable */
183 1 : #define MII_ESTAT_1000BASE_T_HALF BIT(12)
184 :
185 : /* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */
186 : /** DEVAD Mask */
187 1 : #define MII_MMD_ACR_DEVAD_MASK (0x1F << 0)
188 : /** Address Data bits */
189 1 : #define MII_MMD_ACR_ADDR (0x00 << 14)
190 0 : #define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14)
191 0 : #define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14)
192 0 : #define MII_MMD_ACR_DATA_W_POS_INC (0x11 << 14)
193 :
194 : /**
195 : * @}
196 : */
197 :
198 : #endif /* ZEPHYR_INCLUDE_NET_MII_H_ */
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