Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_SYS_BARRIER_H_
       8             : #define ZEPHYR_INCLUDE_SYS_BARRIER_H_
       9             : 
      10             : #include <zephyr/toolchain.h>
      11             : 
      12             : #if defined(CONFIG_BARRIER_OPERATIONS_ARCH)
      13             : # if defined(CONFIG_ARM)
      14             : # include <zephyr/arch/arm/barrier.h>
      15             : # elif defined(CONFIG_ARM64)
      16             : # include <zephyr/arch/arm64/barrier.h>
      17             : # endif
      18             : #elif defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
      19             : #include <zephyr/sys/barrier_builtin.h>
      20             : #endif
      21             : 
      22             : #ifdef __cplusplus
      23             : extern "C" {
      24             : #endif
      25             : 
      26             : /**
      27             :  * @addtogroup barrier_apis Barrier Services APIs
      28             :  * @since 3.4
      29             :  * @version 0.1.0
      30             :  * @ingroup kernel_apis
      31             :  * @{
      32             :  */
      33             : 
      34             : /**
      35             :  * @brief Full/sequentially-consistent data memory barrier.
      36             :  *
      37             :  * This routine acts as a synchronization fence between threads and prevents
      38             :  * re-ordering of data accesses instructions across the barrier instruction.
      39             :  */
      40           1 : static ALWAYS_INLINE void barrier_dmem_fence_full(void)
      41             : {
      42             : #if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
      43             :         z_barrier_dmem_fence_full();
      44             : #endif
      45             : }
      46             : 
      47             : /**
      48             :  * @brief Full/sequentially-consistent data synchronization barrier.
      49             :  *
      50             :  * This routine acts as a synchronization fence between threads and prevents
      51             :  * re-ordering of data accesses instructions across the barrier instruction
      52             :  * like @ref barrier_dmem_fence_full(), but has the additional effect of
      53             :  * blocking execution of any further instructions, not just loads or stores, or
      54             :  * both, until synchronization is complete.
      55             :  *
      56             :  * @note When not supported by hardware or architecture, this instruction falls
      57             :  * back to a full/sequentially-consistent data memory barrier.
      58             :  */
      59           1 : static ALWAYS_INLINE void barrier_dsync_fence_full(void)
      60             : {
      61             : #if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
      62             :         z_barrier_dsync_fence_full();
      63             : #endif
      64             : }
      65             : 
      66             : /**
      67             :  * @brief Full/sequentially-consistent instruction synchronization barrier.
      68             :  *
      69             :  * This routine is used to guarantee that any subsequent instructions are
      70             :  * fetched and to ensure any previously executed context-changing operations,
      71             :  * such as writes to system control registers, have completed by the time the
      72             :  * routine completes. In hardware terms, this might mean that the instruction
      73             :  * pipeline is flushed, for example.
      74             :  *
      75             :  * @note When not supported by hardware or architecture, this instruction falls
      76             :  * back to a compiler barrier.
      77             :  */
      78           1 : static ALWAYS_INLINE void barrier_isync_fence_full(void)
      79             : {
      80             : #if defined(CONFIG_BARRIER_OPERATIONS_ARCH) || defined(CONFIG_BARRIER_OPERATIONS_BUILTIN)
      81             :         z_barrier_isync_fence_full();
      82             : #endif
      83             : }
      84             : 
      85             : /** @} */
      86             : 
      87             : #ifdef __cplusplus
      88             : } /* extern "C" */
      89             : #endif
      90             : 
      91             : #endif /* ZEPHYR_INCLUDE_SYS_ATOMIC_H_ */