Line data Source code
1 1 : /*
2 : * Copyright 2024 Google LLC
3 : * SPDX-License-Identifier: Apache-2.0
4 : */
5 :
6 : #ifndef ZEPHYR_INCLUDE_USB_C_TCPCI_H_
7 : #define ZEPHYR_INCLUDE_USB_C_TCPCI_H_
8 :
9 : /**
10 : * @file
11 : * @brief Registers and fields definitions for TypeC Port Controller Interface
12 : *
13 : * This file contains register addresses, fields and masks used to retrieve specific data from
14 : * registry values. They may be used by all TCPC drivers compliant to the TCPCI specification.
15 : * Registers and fields are compliant to the Type-C Port Controller Interface
16 : * Specification Revision 2.0, Version 1.3.
17 : */
18 :
19 : /** Register address - vendor id */
20 1 : #define TCPC_REG_VENDOR_ID 0x0
21 :
22 : /** Register address - product id */
23 1 : #define TCPC_REG_PRODUCT_ID 0x2
24 :
25 : /** Register address - version of TCPC */
26 1 : #define TCPC_REG_BCD_DEV 0x4
27 :
28 : /** Register address - USB TypeC version */
29 1 : #define TCPC_REG_TC_REV 0x6
30 : /** Mask for major part of type-c release supported */
31 1 : #define TCPC_REG_TC_REV_MAJOR_MASK GENMASK(7, 4)
32 : /** Macro to extract the major part of type-c release supported */
33 1 : #define TCPC_REG_TC_REV_MAJOR(reg) (((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4)
34 : /** Mask for minor part of type-c release supported */
35 1 : #define TCPC_REG_TC_REV_MINOR_MASK GENMASK(3, 0)
36 : /** Macro to extract the minor part of type-c release supported */
37 1 : #define TCPC_REG_TC_REV_MINOR(reg) ((reg) & TCPC_REG_TC_REV_MINOR_MASK)
38 :
39 : /** Register address - Power delivery revision */
40 1 : #define TCPC_REG_PD_REV 0x8
41 : /** Mask for major part of USB PD revision supported */
42 1 : #define TCPC_REG_PD_REV_REV_MAJOR_MASK GENMASK(15, 12)
43 : /** Macro to extract the major part of USB PD revision supported */
44 1 : #define TCPC_REG_PD_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_REV_MAJOR_MASK) >> 12)
45 : /** Mask for minor part of USB PD revision supported */
46 1 : #define TCPC_REG_PD_REV_REV_MINOR_MASK GENMASK(11, 8)
47 : /** Macro to extract the minor part of USB PD revision supported */
48 1 : #define TCPC_REG_PD_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_REV_MINOR_MASK) >> 8)
49 : /** Mask for major part of USB PD version supported */
50 1 : #define TCPC_REG_PD_REV_VER_MAJOR_MASK GENMASK(7, 4)
51 : /** Macro to extract the major part of USB PD version supported */
52 1 : #define TCPC_REG_PD_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_MAJOR_MASK) >> 4)
53 : /** Mask for minor part of USB PD version supported */
54 1 : #define TCPC_REG_PD_REV_VER_MINOR_MASK GENMASK(3, 0)
55 : /** Macro to extract the minor part of USB PD version supported */
56 1 : #define TCPC_REG_PD_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_MINOR_MASK)
57 :
58 : /** Register address - interface revision and version */
59 1 : #define TCPC_REG_PD_INT_REV 0xa
60 : /** Mask for major part of USB Port Controller Interface revision supported */
61 1 : #define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK GENMASK(15, 12)
62 : /** Macro to extract the major part of USB Port Controller Interface revision supported */
63 1 : #define TCPC_REG_PD_INT_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_INT_REV_REV_MAJOR_MASK) >> 12)
64 : /** Mask for minor part of USB Port Controller Interface revision supported */
65 1 : #define TCPC_REG_PD_INT_REV_REV_MINOR_MASK GENMASK(11, 8)
66 : /** Macro to extract the minor part of USB Port Controller Interface revision supported */
67 1 : #define TCPC_REG_PD_INT_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_INT_REV_REV_MINOR_MASK) >> 8)
68 : /** Mask for major part of USB Port Controller Interface version supported */
69 1 : #define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK GENMASK(7, 4)
70 : /** Macro to extract the major part of USB Port Controller Interface version supported */
71 1 : #define TCPC_REG_PD_INT_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_INT_REV_VER_MAJOR_MASK) >> 4)
72 : /** Mask for minor part of USB Port Controller Interface version supported */
73 1 : #define TCPC_REG_PD_INT_REV_VER_MINOR_MASK GENMASK(3, 0)
74 : /** Macro to extract the minor part of USB Port Controller Interface version supported */
75 1 : #define TCPC_REG_PD_INT_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_INT_REV_VER_MINOR_MASK)
76 :
77 : /** Register address - alert */
78 1 : #define TCPC_REG_ALERT 0x10
79 : /** Value for clear alert */
80 1 : #define TCPC_REG_ALERT_NONE 0x0000
81 : /** Value mask for all alert bits */
82 1 : #define TCPC_REG_ALERT_MASK_ALL 0xffff
83 : /** Bit for vendor defined alert */
84 1 : #define TCPC_REG_ALERT_VENDOR_DEF BIT(15)
85 : /** Bit for extended alert */
86 1 : #define TCPC_REG_ALERT_ALERT_EXT BIT(14)
87 : /** Bit for extended status alert */
88 1 : #define TCPC_REG_ALERT_EXT_STATUS BIT(13)
89 : /** Bit for beginning of data receive */
90 1 : #define TCPC_REG_ALERT_RX_BEGINNING BIT(12)
91 : /** Bit for vbus disconnection alert */
92 1 : #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
93 : /** Bit for receive buffer overflow alert */
94 1 : #define TCPC_REG_ALERT_RX_BUF_OVF BIT(10)
95 : /** Bit for fault alert */
96 1 : #define TCPC_REG_ALERT_FAULT BIT(9)
97 : /** Bit for low vbus alarm */
98 1 : #define TCPC_REG_ALERT_V_ALARM_LO BIT(8)
99 : /** Bit for high vbus alarm */
100 1 : #define TCPC_REG_ALERT_V_ALARM_HI BIT(7)
101 : /** Bit for transmission success */
102 1 : #define TCPC_REG_ALERT_TX_SUCCESS BIT(6)
103 : /** Bit for transmission discard alert */
104 1 : #define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
105 : /** Bit for transmission fail alert */
106 1 : #define TCPC_REG_ALERT_TX_FAILED BIT(4)
107 : /** Bit for received hard reset alert */
108 1 : #define TCPC_REG_ALERT_RX_HARD_RST BIT(3)
109 : /** Bit for data received alert */
110 1 : #define TCPC_REG_ALERT_RX_STATUS BIT(2)
111 : /** Bit for power status alert */
112 1 : #define TCPC_REG_ALERT_POWER_STATUS BIT(1)
113 : /** Bit for CC lines status alert */
114 1 : #define TCPC_REG_ALERT_CC_STATUS BIT(0)
115 : /** Bits for any of transmission status alert */
116 1 : #define TCPC_REG_ALERT_TX_COMPLETE \
117 : (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED)
118 :
119 : /**
120 : * Register address - alert mask
121 : * The bits for specific masks are on the same positions as for the @see TCPC_REG_ALERT register.
122 : */
123 1 : #define TCPC_REG_ALERT_MASK 0x12
124 :
125 : /**
126 : * Register address - power status mask
127 : * The bits for specific masks are on the same positions as for the @see TCPC_REG_POWER_STATUS
128 : * register.
129 : */
130 1 : #define TCPC_REG_POWER_STATUS_MASK 0x14
131 :
132 : /**
133 : * Register address - fault status mask
134 : * The bits for specific masks are on the same positions as for the @see TCPC_REG_FAULT_STATUS
135 : * register.
136 : */
137 1 : #define TCPC_REG_FAULT_STATUS_MASK 0x15
138 :
139 : /**
140 : * Register address - extended status mask
141 : * The bits for specific masks are on the same positions as for the @see TCPC_REG_EXT_STATUS
142 : * register.
143 : */
144 1 : #define TCPC_REG_EXT_STATUS_MASK 0x16
145 :
146 : /**
147 : * Register address - extended alert mask
148 : * The bits for specific masks are on the same positions as for the @see TCPC_REG_ALERT_EXT
149 : * register.
150 : */
151 1 : #define TCPC_REG_ALERT_EXT_MASK 0x17
152 :
153 : /** Register address - configure standard output */
154 1 : #define TCPC_REG_CONFIG_STD_OUTPUT 0x18
155 : /** Bit for high impedance outputs */
156 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z BIT(7)
157 : /** Bit for debug accessory connected# */
158 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6)
159 : /** Bit for audio accessory connected# */
160 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5)
161 : /** Bit for active cable */
162 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE BIT(4)
163 : /** Value mask for mux control */
164 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2)
165 : /** Value for mux - no connection */
166 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2)
167 : /** Value for mux - USB3.1 connected */
168 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB (1 << 2)
169 : /** Value for mux - DP alternate mode with 4 lanes */
170 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2)
171 : /** Value for mux - USB3.1 + DP 0&1 lines */
172 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP (3 << 2)
173 : /** Bit for connection present */
174 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT BIT(1)
175 : /** Bit for connector orientation */
176 1 : #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
177 :
178 : /** Register address - TCPC control */
179 1 : #define TCPC_REG_TCPC_CTRL 0x19
180 : /** Bit for SMBus PEC enabled */
181 1 : #define TCPC_REG_TCPC_CTRL_SMBUS_PEC BIT(7)
182 : /** Bit for enabling the alert assertion when a connection is found */
183 1 : #define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6)
184 : /** Bit for watchdog monitoring */
185 1 : #define TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER BIT(5)
186 : /** Bit for enable debug accessory control by TCPM */
187 1 : #define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4)
188 : /** Mask*/
189 1 : #define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK GENMASK(3, 2)
190 : /** Value for clock stretching disabled */
191 1 : #define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED 0
192 : /** Value for limited clock stretching enabled */
193 1 : #define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS (2 << 2)
194 : /** Value for clock stretching enabled only when alert is NOT asserted */
195 1 : #define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT (3 << 2)
196 : /** Bit for BIST test mode enabled */
197 1 : #define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1)
198 : /** Bit for plug orientation and vconn destination */
199 1 : #define TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION BIT(0)
200 :
201 : /** Register address - role control */
202 1 : #define TCPC_REG_ROLE_CTRL 0x1a
203 : /** Bit for dual-role port */
204 1 : #define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
205 : /** Mask to extract the RP value from register value */
206 1 : #define TCPC_REG_ROLE_CTRL_RP_MASK GENMASK(5, 4)
207 : /** Mask to extract the CC2 pull value from register value */
208 1 : #define TCPC_REG_ROLE_CTRL_CC2_MASK GENMASK(3, 2)
209 : /** Mask to extract the CC! pull value from register value */
210 1 : #define TCPC_REG_ROLE_CTRL_CC1_MASK GENMASK(1, 0)
211 : /** Macro to set the register value from drp, rp and CC lines values */
212 1 : #define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
213 : ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
214 : (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \
215 : (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))
216 0 : #define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
217 : /** Macro to extract the enum tc_rp_value from register value */
218 1 : #define TCPC_REG_ROLE_CTRL_RP(reg) (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
219 : /** Macro to extract the enum tc_cc_pull for CC2 from register value */
220 1 : #define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
221 : /** Macro to extract the enum tc_cc_pull for CC1 from register value */
222 1 : #define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
223 :
224 : /** Register address - fault control */
225 1 : #define TCPC_REG_FAULT_CTRL 0x1b
226 : /** Bit for block the standard input signal force off vbus control */
227 1 : #define TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF BIT(4)
228 : /** Bit for disabling the vbus discharge fault detection timer */
229 1 : #define TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT BIT(3)
230 : /** Bit for disabling the vbus over current detection */
231 1 : #define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(2)
232 : /** Bit for disabling the vbus over voltage detection */
233 1 : #define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1)
234 : /** Bit for disabling the vconn over current detection */
235 1 : #define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS BIT(0)
236 :
237 : /** Register address - power control */
238 1 : #define TCPC_REG_POWER_CTRL 0x1c
239 : /** Bit for fast role swap enable */
240 1 : #define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7)
241 : /** Bit for disabling the vbus voltage monitoring */
242 1 : #define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6)
243 : /** Bit for disabling the voltage alarms */
244 1 : #define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5)
245 : /** Bit for enabling the automatic vbus discharge based on the vbus voltage */
246 1 : #define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
247 : /** Bit for enabling the bleed discharge of vbus */
248 1 : #define TCPC_REG_POWER_CTRL_BLEED_DISCHARGE BIT(3)
249 : /** Bit for enabling the forced vbus discharge */
250 1 : #define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2)
251 : /**
252 : * Bit for enabling the vconn power supported.
253 : * If set, the TCPC will deliver at least the power indicated in the vconn power supported in
254 : * device capabilities register to the vconn.
255 : * If unset, at least 1W of power will be delivered to vconn.
256 : */
257 1 : #define TCPC_REG_POWER_CTRL_VCONN_SUPP BIT(1)
258 : /** Bit for enabling the vconn sourcing to CC line */
259 1 : #define TCPC_REG_POWER_CTRL_VCONN_EN BIT(0)
260 :
261 : /** Register address - CC lines status */
262 1 : #define TCPC_REG_CC_STATUS 0x1d
263 : /** Bit for active looking for a connection by TCPC, both DRP and sink/source only */
264 1 : #define TCPC_REG_CC_STATUS_LOOK4CONNECTION BIT(5)
265 : /** Bit for connection result, set if presenting Rd, unset if presenting Rp*/
266 1 : #define TCPC_REG_CC_STATUS_CONNECT_RESULT BIT(4)
267 : /** Mask for CC2 line state */
268 1 : #define TCPC_REG_CC_STATUS_CC2_STATE_MASK GENMASK(3, 2)
269 : /**
270 : * Macro to extract the status value of CC2 line. Interpretation of this value depends on the
271 : * value of CC2 configuration in Role Control register and on the connect result in this register.
272 : * For value interpretation look at the CC_STATUS Register Definition in the TCPCI specification.
273 : */
274 1 : #define TCPC_REG_CC_STATUS_CC2_STATE(reg) (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
275 : /** Mask for CC1 line state */
276 1 : #define TCPC_REG_CC_STATUS_CC1_STATE_MASK GENMASK(1, 0)
277 : /** Macto to extract the status value of CC1 line. Look at the information about the CC2 macro. */
278 1 : #define TCPC_REG_CC_STATUS_CC1_STATE(reg) ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
279 :
280 : /** Register address - power status */
281 1 : #define TCPC_REG_POWER_STATUS 0x1e
282 : /** Bit for debug accessory connected */
283 1 : #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
284 : /** Bit for internal initialization in-progress. If set, only registers 00-0F contain valid data. */
285 1 : #define TCPC_REG_POWER_STATUS_UNINIT BIT(6)
286 : /** Bit for sourcing high voltage. If set, the voltage sourced is above the vSafe5V. */
287 1 : #define TCPC_REG_POWER_STATUS_SOURCING_HV BIT(5)
288 : /** Bit for sourcing vbus. If set, sourcing vbus is enabled. */
289 1 : #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
290 : /** Bit for vbus detection enabled. */
291 1 : #define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3)
292 : /**
293 : * Bit for vbus present.
294 : * If set, the vbus shall be above 4V. If unset, the vbus shall be below 3.5V.
295 : */
296 1 : #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
297 : /** Bit for vconn present. Set if vconn is present on CC1 or CC2, threshold is fixed at 2.4V. */
298 1 : #define TCPC_REG_POWER_STATUS_VCONN_PRES BIT(1)
299 : /** Bit for sinking vbus. If set, the TCPC is sinking vbus to the system load. */
300 1 : #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
301 :
302 : /** Register address - fault status */
303 1 : #define TCPC_REG_FAULT_STATUS 0x1f
304 : /** Bit for all registers reset to default */
305 1 : #define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7)
306 : /** Bit for force vbus off due to external fault */
307 1 : #define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6)
308 : /** Bit for auto discharge failed */
309 1 : #define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5)
310 : /** Bit for force discharge failed */
311 1 : #define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
312 : /** Bit for internal or external vbus over current */
313 1 : #define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3)
314 : /** Bit for internal or external vbus over voltage */
315 1 : #define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2)
316 : /** Bit for vconn over current */
317 1 : #define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1)
318 : /** Bit for I2C interface error */
319 1 : #define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0)
320 :
321 : /** Register address - extended status */
322 1 : #define TCPC_REG_EXT_STATUS 0x20
323 : /** Bit for vbus at vSafe0V. Set when the TCPC detects that VBUS is below 0.8V. */
324 1 : #define TCPC_REG_EXT_STATUS_SAFE0V BIT(0)
325 :
326 : /** Register address - alert extended */
327 1 : #define TCPC_REG_ALERT_EXT 0x21
328 : /** Bit for timer expired */
329 1 : #define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
330 : /** Bit for source fast role swap. Set when FRS signal sent due to standard input being low. */
331 1 : #define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1)
332 : /** Bit for sink fast role swap. If set, the fast role swap signal was received. */
333 1 : #define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0)
334 :
335 : /** Register address - command */
336 1 : #define TCPC_REG_COMMAND 0x23
337 : /** Value for wake i2c command */
338 1 : #define TCPC_REG_COMMAND_WAKE_I2C 0x11
339 : /** Value for disable vbus detect command - disable vbus present and vSafe0V detection */
340 1 : #define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT 0x22
341 : /** Value for enable vbus detect command - enable vbus present and vSafe0V detection */
342 1 : #define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33
343 : /** Value for disable sink vbus - disable sinking power over vbus */
344 1 : #define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44
345 : /** Value for sink vbus - enable sinking power over vbus and vbus present detection */
346 1 : #define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55
347 : /** Value for disable source vbus - disable sourcing power over vbus */
348 1 : #define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66
349 : /** Value for source vbus default voltage - enable sourcing vSafe5V over vbus */
350 1 : #define TCPC_REG_COMMAND_SRC_CTRL_DEF 0x77
351 : /** Value for source vbus high voltage - enable sourcing high voltage over vbus */
352 1 : #define TCPC_REG_COMMAND_SRC_CTRL_HV 0x88
353 : /** Value for look for connection - start DRP toggling if DRP role is set */
354 1 : #define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99
355 : /**
356 : * Value for rx one more
357 : * Configure receiver to automatically clear the receive_detect register after sending next GoodCRC.
358 : */
359 1 : #define TCPC_REG_COMMAND_RX_ONE_MORE 0xAA
360 : /**
361 : * Value for send fast role swap signal
362 : * Send FRS if TCPC is source with FRS enabled in power control register
363 : */
364 1 : #define TCPC_REG_COMMAND_SEND_FRS_SIGNAL 0xCC
365 : /** Value for reset transmit buffer - TCPC resets the pointer of transmit buffer to offset 1 */
366 1 : #define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD
367 : /**
368 : * Value for reset receive buffer
369 : * If buffer pointer is at 132 or less, it is reset to 1, otherwise it is reset to 133.
370 : */
371 1 : #define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE
372 : /** Value for i2c idle */
373 1 : #define TCPC_REG_COMMAND_I2CIDLE 0xFF
374 :
375 : /** Register address - device capabilities 1 */
376 1 : #define TCPC_REG_DEV_CAP_1 0x24
377 : /** Bit for vbus high voltage target - if set, VBUS_HV_TARGET register is implemented */
378 1 : #define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15)
379 : /** Bit for vbus over current reporting - if set, vbus over current is reported by TCPC */
380 1 : #define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14)
381 : /** Bit for vbus over voltage reporting - if set, vbus over voltage is reported by TCPC */
382 1 : #define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13)
383 : /** Bit for bleed discharge - if set, bleed discharge is implemented in TCPC */
384 1 : #define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12)
385 : /** Bit for force discharge - if set, force discharge is implemented in TCPC */
386 1 : #define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11)
387 : /**
388 : * Bit for vbus measurement and alarm capable
389 : * If set, TCPC supports vbus voltage measurement and vbus voltage alarms
390 : */
391 1 : #define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10)
392 : /** Mask for source resistor supported */
393 1 : #define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK GENMASK(9, 8)
394 : /**
395 : * Macro to extract the supported source resistors from register value
396 : * The value can be cast to enum tc_rp_value and value can be treated as highest amperage supported
397 : * since the TCPC has also to support lower values than specified.
398 : */
399 1 : #define TCPC_REG_DEV_CAP_1_SRC_RESISTOR(reg) \
400 : (((reg) & TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK) >> 8)
401 : /** Value for Rp default only - only default amperage is supported */
402 1 : #define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF 0
403 : /** Value for Rp 1.5A and default - support for 1.5A and for default amperage*/
404 1 : #define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF 1
405 : /** Value for Rp 3.0A, 1.5A and default - support for 3.0A, 1.5A and default amperage */
406 1 : #define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF 2
407 : /** Mask for power roles supported */
408 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK GENMASK(7, 5)
409 0 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE(reg) \
410 : (((reg) & TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK) >> 5)
411 : /** Value for support both source and sink only (no DRP) */
412 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK 0
413 : /** Value for support source role only */
414 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC 1
415 : /** Value for support sink role only */
416 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK 2
417 : /** Value for support sink role with accessory */
418 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC 3
419 : /** Value for support dual-role port only */
420 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP 4
421 : /** Value for support source, sink, dual-role port, adapter and cable */
422 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL 5
423 : /** Value for support source, sink and dual-role port */
424 1 : #define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP 6
425 : /** Bit for debug SOP' and SOP'' support - if set, all SOP* messages are supported */
426 1 : #define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4)
427 : /** Bit for source vconn - if set, TCPC is capable of switching the vconn source */
428 1 : #define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3)
429 : /** Bit for sink vbus - if set, TCPC is capable of controling the sink path to the system load */
430 1 : #define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2)
431 : /**
432 : * Bit for source high voltage vbus.
433 : * If set, TCPC can control the source high voltage path to vbus
434 : */
435 1 : #define TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS BIT(1)
436 : /** Bit for source vbus - if set, TCPC is capable of controlling the source path to vbus */
437 1 : #define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0)
438 :
439 : /** Register address - device capabilities 2 */
440 1 : #define TCPC_REG_DEV_CAP_2 0x26
441 : /** Bit for device capabilities 3 support */
442 1 : #define TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED BIT(15)
443 : /** Bit for message disable disconnect */
444 1 : #define TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT BIT(14)
445 : /** Bit for generic timer support */
446 1 : #define TCPC_REG_DEV_CAP_2_GENERIC_TIMER BIT(13)
447 : /**
448 : * Bit for long message support
449 : * If set, the TCPC supports up to 264 bytes content of the SOP*.
450 : * One I2C transaction can write up to 132 bytes.
451 : * If unset, the TCPC support only 30 bytes content of the SOP* message.
452 : */
453 1 : #define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12)
454 : /** Bit for SMBus PEC support. If set, SMBus PEC can be enabled in the TCPC control register. */
455 1 : #define TCPC_REG_DEV_CAP_2_SMBUS_PEC BIT(11)
456 : /** Bit for source fast-role swap support. If set, TCPC is capable of sending FRS as source. */
457 1 : #define TCPC_REG_DEV_CAP_2_SRC_FRS BIT(10)
458 : /** Bit for sink fast-role swap support. If set, TCPC is capable of sending FRS as sink. */
459 1 : #define TCPC_REG_DEV_CAP_2_SNK_FRS BIT(9)
460 : /** Bit for watchdog timer support. If set, watchdog can be enabled in the TCPC control register. */
461 1 : #define TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER BIT(8)
462 : /**
463 : * Bit for sink disconnect detection.
464 : * If set, the sink disconnect threshold can be set. Otherwise, the vbus present value from
465 : * status register will be used to indicate the sink disconnection.
466 : */
467 1 : #define TCPC_REG_DEV_CAP_2_SNK_DISC_DET BIT(7)
468 : /**
469 : * Bit for stop discharge threshold. If set, the TCPM can set the voltage threshold at which
470 : * the forced vbus discharge will be disabled, into the vbus stop discharge threshold register.
471 : */
472 1 : #define TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH BIT(6)
473 : /** Mask for resolution of voltage alarm */
474 1 : #define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK GENMASK(5, 4)
475 : /** Macro to extract the voltage alarm resolution from the register value */
476 1 : #define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM(reg) \
477 : (((reg) & TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK) >> 4)
478 : /** Value for 25mV resolution of voltage alarm, all 10 bits of voltage alarm registers are used. */
479 1 : #define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV 0
480 : /** Value for 50mV resolution of voltage alarm, only 9 bits of voltage alarm registers are used. */
481 1 : #define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV 1
482 : /** Value for 100mV resolution of voltage alarm, only 8 bits of voltage alarm registers are used. */
483 1 : #define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV 2
484 : /** Mask for vconn power supported */
485 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK GENMASK(3, 1)
486 : /** Macro to extract the vconn power supported from the register value */
487 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED(reg) \
488 : (((reg) & TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK) >> 1)
489 : /** Value for vconn power supported of 1.0W */
490 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W 0
491 : /** Value for vconn power supported of 1.5W */
492 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W 1
493 : /** Value for vconn power supported of 2.0W */
494 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W 2
495 : /** Value for vconn power supported of 3.0W */
496 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W 3
497 : /** Value for vconn power supported of 4.0W */
498 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W 4
499 : /** Value for vconn power supported of 5.0W */
500 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W 5
501 : /** Value for vconn power supported of 6.0W */
502 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W 6
503 : /** Value for external vconn power supported */
504 1 : #define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL 7
505 : /** Bit for vconn overcurrent fault capable - if set, TCPC can detect the vconn over current */
506 1 : #define TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT BIT(0)
507 :
508 : /** Register address - standard input capabilities */
509 1 : #define TCPC_REG_STD_INPUT_CAP 0x28
510 : /** Mask for source fast role swap */
511 1 : #define TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK GENMASK(4, 3)
512 : /** Macro to extract the source fast role swap from register value */
513 1 : #define TCPC_REG_STD_INPUT_CAP_SRC_FRS(reg) (((reg) & TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK) >> 3)
514 : /** Value for no source fast role swap pin present in TCPC */
515 1 : #define TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE 0
516 : /** Value for source fast role swap input only pin present in TCPC */
517 1 : #define TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT 1
518 : /** Value for source fast role swap both input and output pin present in TCPC */
519 1 : #define TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH 2
520 : /** Bit for vbus external over voltage fault. If set, input pin is present in TCPC. */
521 1 : #define TCPC_REG_STD_INPUT_CAP_EXT_OVP BIT(2)
522 : /** Bit for vbus external over current fault. If set, input pin is present in TCPC. */
523 1 : #define TCPC_REG_STD_INPUT_CAP_EXT_OCP BIT(1)
524 : /** Bit for force off vbus present. If set, input pin is present in TCPC. */
525 1 : #define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0)
526 :
527 : /** Register address - standard output capabilities */
528 1 : #define TCPC_REG_STD_OUTPUT_CAP 0x29
529 : /** Bit for vbus sink disconnect detect indicator */
530 1 : #define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7)
531 : /** Bit for debug accessory indicator */
532 1 : #define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6)
533 : /** Bit for vbus present monitor */
534 1 : #define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5)
535 : /** Bit for audio adapter accessory indicator */
536 1 : #define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4)
537 : /** Bit for active cable indicator */
538 1 : #define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3)
539 : /** Bit for mux configuration control */
540 1 : #define TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL BIT(2)
541 : /** Bit for connection present */
542 1 : #define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1)
543 : /** Bit for connector orientation */
544 1 : #define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0)
545 :
546 : /** Register address - configure extended 1 */
547 1 : #define TCPC_REG_CONFIG_EXT_1 0x2A
548 : /**
549 : * Bit for fr swap bidirectional pin.
550 : * If set, the bidirectional FR swap pin is configured as standard output signal.
551 : * If unset, it's configured as standard input signal.
552 : */
553 1 : #define TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR BIT(1)
554 : /**
555 : * Bit for standard input source FR swap.
556 : * If set, blocks the source fast role swap input signal from triggering the sending of
557 : * fast role swap signal.
558 : * If unset, allow the input signal to trigger sending the fast role swap signal.
559 : */
560 1 : #define TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS BIT(0)
561 :
562 : /**
563 : * Register address - generic timer
564 : * Available only if generic timer bit is set in device capabilities 2 register.
565 : * This register is 16-bit wide and has a resolution of 0.1ms.
566 : */
567 1 : #define TCPC_REG_GENERIC_TIMER 0x2c
568 :
569 : /** Register address - message header info */
570 1 : #define TCPC_REG_MSG_HDR_INFO 0x2e
571 : /** Bit for cable plug. If set, the message originated from a cable plug. */
572 1 : #define TCPC_REG_MSG_HDR_INFO_CABLE_PLUG BIT(4)
573 : /** Mask for data role */
574 1 : #define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK BIT(3)
575 : /** Macro to extract the data role from register value */
576 1 : #define TCPC_REG_MSG_HDR_INFO_DATA_ROLE(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK) >> 3)
577 : /** Value for data role set as UFP */
578 1 : #define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP 0
579 : /** Value for data role set as DFP */
580 1 : #define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP 1
581 : /** Mask for Power Delivery Specification Revision */
582 1 : #define TCPC_REG_MSG_HDR_INFO_PD_REV_MASK GENMASK(2, 1)
583 : /** Macro to extract the Power Delivery Specification Revision from register value */
584 1 : #define TCPC_REG_MSG_HDR_INFO_PD_REV(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_PD_REV_MASK) >> 1)
585 : /** Value for Power Delivery Specification Revision 1.0 */
586 1 : #define TCPC_REG_MSG_HDR_INFO_PD_REV_1_0 0
587 : /** Value for Power Delivery Specification Revision 2.0 */
588 1 : #define TCPC_REG_MSG_HDR_INFO_PD_REV_2_0 1
589 : /** Value for Power Delivery Specification Revision 3.0 */
590 1 : #define TCPC_REG_MSG_HDR_INFO_PD_REV_3_0 2
591 : /** Mask for power role */
592 1 : #define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK BIT(0)
593 : /** Macro to extract the power role from register value */
594 1 : #define TCPC_REG_MSG_HDR_INFO_POWER_ROLE(reg) ((reg) & TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK)
595 : /** Value for power role set as sink */
596 1 : #define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK 0
597 : /** Value for power role set as source */
598 1 : #define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC 1
599 : /**
600 : * Macro to set the register value with pd revision, data and power role from parameter and as
601 : * non-cable plug
602 : */
603 1 : #define TCPC_REG_MSG_HDR_INFO_SET(pd_rev_type, drole, prole) \
604 : ((drole) << 3 | (pd_rev_type << 1) | (prole))
605 : /** Mask for PD revision and power and data role */
606 1 : #define TCPC_REG_MSG_HDR_INFO_ROLES_MASK (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1))
607 :
608 : /** Register address - receive detect */
609 1 : #define TCPC_REG_RX_DETECT 0x2f
610 : /**
611 : * Bit for message disable disconnect.
612 : * If set, the TCPC set as sink shall disable the PD message delivery when the SNK.Open state
613 : * is detected for debounce time specified in specification.
614 : * If unset, sink TCPC disables the PD message delivery when vbus sink disconnect detected in
615 : * alert register is asserted.
616 : */
617 1 : #define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7)
618 : /** Bit for enable cable reset. If set, TCPC will detect the cable reset signal. */
619 1 : #define TCPC_REG_RX_DETECT_CABLE_RST BIT(6)
620 : /** Bit for enable hard reset. If set, TCPC will detect the hard reset signal. */
621 1 : #define TCPC_REG_RX_DETECT_HRST BIT(5)
622 : /** Bit for enable SOP_DBG'' message. If set, TCPC will detect the SOP_DBG'' messages. */
623 1 : #define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4)
624 : /** Bit for enable SOP_DBG' message. If set, TCPC will detect the SOP_DBG' messages. */
625 1 : #define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3)
626 : /** Bit for enable SOP'' message. If set, TCPC will detect the SOP'' messages. */
627 1 : #define TCPC_REG_RX_DETECT_SOPPP BIT(2)
628 : /** Bit for enable SOP' message. If set, TCPC will detect the SOP' messages. */
629 1 : #define TCPC_REG_RX_DETECT_SOPP BIT(1)
630 : /** Bit for enable SOP message. If set, TCPC will detect the SOP messages. */
631 1 : #define TCPC_REG_RX_DETECT_SOP BIT(0)
632 : /** Mask for detecting the SOP messages and hard reset signals */
633 1 : #define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
634 : /** Mask for detecting the SOP, SOP' and SOP'' messages and hard reset signals */
635 1 : #define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \
636 : (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | TCPC_REG_RX_DETECT_SOPPP | \
637 : TCPC_REG_RX_DETECT_HRST)
638 :
639 : /**
640 : * Register address - receive buffer (readable byte count, rx buf frame type, rx buf byte x)
641 : * In TCPC Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
642 : * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
643 : * only be accessed by reading at a common register address 30h.
644 : */
645 1 : #define TCPC_REG_RX_BUFFER 0x30
646 :
647 : /** Register address - transmit */
648 1 : #define TCPC_REG_TRANSMIT 0x50
649 : /** Macro to set the transmit register with message type and retries count */
650 1 : #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) ((retries) << 4 | (type))
651 : /** Macro to set the transmit register with message type and without retries */
652 1 : #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
653 : /** Value for transmit SOP type message */
654 1 : #define TCPC_REG_TRANSMIT_TYPE_SOP 0
655 : /** Value for transmit SOP' type message */
656 1 : #define TCPC_REG_TRANSMIT_TYPE_SOPP 1
657 : /** Value for transmit SOP'' type message */
658 1 : #define TCPC_REG_TRANSMIT_TYPE_SOPPP 2
659 : /** Value for transmit SOP_DBG' type message */
660 1 : #define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P 3
661 : /** Value for transmit SOP_DBG'' type message */
662 1 : #define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP 4
663 : /** Value for transmit hard reset signal */
664 1 : #define TCPC_REG_TRANSMIT_TYPE_HRST 5
665 : /** Value for transmit cable reset signal */
666 1 : #define TCPC_REG_TRANSMIT_TYPE_CABLE_RST 6
667 : /** Value for transmit BIST carrier mode 2 */
668 1 : #define TCPC_REG_TRANSMIT_TYPE_BIST 7
669 :
670 : /**
671 : * Register address - transmit buffer
672 : * In TCPC Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
673 : * portion of the SOP* USB PD message payload (including the header and/or the
674 : * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
675 : * is “hidden” and can only be accessed by writing to register address 51h
676 : */
677 1 : #define TCPC_REG_TX_BUFFER 0x51
678 :
679 : /** Register address - vbus voltage */
680 1 : #define TCPC_REG_VBUS_VOLTAGE 0x70
681 : /** Mask for vbus voltage measurement */
682 1 : #define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK GENMASK(9, 0)
683 : /** Macro to extract the vbus measurement from the register value */
684 1 : #define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(reg) ((reg) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK)
685 : /** Mask for scale factor */
686 1 : #define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK GENMASK(11, 10)
687 : /** Macro to extract the vbus voltage scale from the register value */
688 1 : #define TCPC_REG_VBUS_VOLTAGE_SCALE(reg) \
689 : (1 << (((reg) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK) >> 10))
690 : /** Resolution of vbus voltage measurement. It's specified as 25mV. */
691 1 : #define TCPC_REG_VBUS_VOLTAGE_LSB 25
692 : /**
693 : * Macro to convert the register value into real voltage measurement taking scale
694 : * factor into account
695 : */
696 1 : #define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \
697 : (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(x) * \
698 : TCPC_REG_VBUS_VOLTAGE_LSB)
699 :
700 : /** Register address - vbus sink disconnect threshold */
701 1 : #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
702 : /**
703 : * Resolution of the value stored in register.
704 : * Value read from register must be multiplied by this value to get a real voltage in mV.
705 : * Voltage in mV written to register must be divided by this constant.
706 : * Specification defines it as 25mV
707 : */
708 1 : #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB 25
709 : /** Mask for the valid bits of voltage trip point */
710 1 : #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK GENMASK(11, 0)
711 : /** Default value for vbus sink disconnect threshold */
712 1 : #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */
713 :
714 : /** Register address - vbus sink disconnect threshold */
715 1 : #define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74
716 : /**
717 : * Resolution of the value stored in register.
718 : * Value read from register must be multiplied by this value to get a real voltage in mV.
719 : * Voltage in mV written to register must be divided by this constant.
720 : * Specification defines it as 25mV.
721 : */
722 1 : #define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB 25
723 : /** Mask for the valid bits of voltage trip point */
724 1 : #define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK GENMASK(11, 0)
725 : /** Default value for vbus stop discharge threshold */
726 1 : #define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT 0x0020 /* 0.8 V */
727 :
728 : /** Register address - vbus voltage alarm - high */
729 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
730 : /**
731 : * Resolution of the value stored in register.
732 : * Value read from register must be multiplied by this value to get a real voltage in mV.
733 : * Voltage in mV written to register must be divided by this constant.
734 : * Specification defines it as 25mV
735 : */
736 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB 25
737 : /** Mask for the valid bits of voltage trip point */
738 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK GENMASK(11, 0)
739 :
740 : /** Register address - vbus voltage alarm - low */
741 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
742 : /**
743 : * Resolution of the value stored in register.
744 : * Value read from register must be multiplied by this value to get a real voltage in mV.
745 : * Voltage in mV written to register must be divided by this constant.
746 : * Specification defines it as 25mV
747 : */
748 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB 25
749 : /** Mask for the valid bits of voltage trip point */
750 1 : #define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK GENMASK(11, 0)
751 :
752 : /**
753 : * Register address - vbus nondefault target
754 : * Available only if vbus nondefault target is asserted in device capabilities 1 register.
755 : * Purpose of this register is to provide value for nondefault voltage over vbus when sending
756 : * the source vbus nondefault voltage command to command register.
757 : */
758 1 : #define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a
759 : /**
760 : * Resolution of the value stored in register.
761 : * Value read from register must be multiplied by this value to get a real voltage in mV.
762 : * Voltage in mV written to register must be divided by this constant.
763 : * Specification defines it as 20mV
764 : */
765 1 : #define TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB 20
766 :
767 : /** Register address - device capabilities 3 */
768 1 : #define TCPC_REG_DEV_CAP_3 0x7c
769 : /** Mask for vbus voltage support */
770 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK GENMASK(2, 0)
771 : /** Macro to extract the vbus voltage support from register value */
772 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX(reg) ((reg) & TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK)
773 : /** Value for nominal voltage supported of 5V */
774 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_5V 0
775 : /** Value for nominal voltage supported of 9V */
776 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_9V 1
777 : /** Value for nominal voltage supported of 15V */
778 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_15V 2
779 : /** Value for nominal voltage supported of 20V */
780 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_20V 3
781 : /** Value for nominal voltage supported of 28V */
782 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_28V 4
783 : /** Value for nominal voltage supported of 36V */
784 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_36V 5
785 : /** Value for nominal voltage supported of 48V */
786 1 : #define TCPC_REG_DEV_CAP_3_VBUS_MAX_48V 6
787 :
788 : #endif /* ZEPHYR_INCLUDE_USB_C_TCPCI_H_ */
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