7#ifndef INTERRUPT_UTIL_H_
8#define INTERRUPT_UTIL_H_
10#if defined(CONFIG_CPU_CORTEX_M)
11#include <cmsis_core.h>
17 for (i = initial_offset - 1; i >= 0; i--) {
19 if (NVIC_GetEnableIRQ(i) == 0) {
29 NVIC_SetPendingIRQ(i);
31 if (NVIC_GetPendingIRQ(i)) {
37 NVIC_ClearPendingIRQ(i);
39 if (!NVIC_GetPendingIRQ(i)) {
58static inline void trigger_irq(
int irq)
60 printk(
"Triggering irq : %d\n", irq);
61#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
62 || defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M1)\
63 || defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
65 NVIC_SetPendingIRQ(irq);
71#elif defined(CONFIG_GIC)
75static inline void trigger_irq(
int irq)
77 printk(
"Triggering irq : %d\n", irq);
80 zassert_true(irq <= 15,
"%u is not a valid SGI interrupt ID", irq);
86#if CONFIG_GIC_VER <= 2
97#elif defined(CONFIG_ARC)
98static inline void trigger_irq(
int irq)
100 printk(
"Triggering irq : %d\n", irq);
101 z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
104#elif defined(CONFIG_X86)
108#define VECTOR_MASK 0xFF
111#define LOAPIC_ICR_IPI_TEST 0x00004000U
133static inline void trigger_irq(
int vector)
146 z_loapic_ipi(cpu_id, LOAPIC_ICR_IPI_TEST, vector);
153 for (i = 0; i < 10; i++) {
158#elif defined(CONFIG_ARCH_POSIX)
161static inline void trigger_irq(
int irq)
166#elif defined(CONFIG_RISCV)
167#if defined(CONFIG_NUCLEI_ECLIC) || defined(CONFIG_NRFX_CLIC)
168void riscv_clic_irq_set_pending(
uint32_t irq);
169static inline void trigger_irq(
int irq)
171 riscv_clic_irq_set_pending(irq);
174static inline void trigger_irq(
int irq)
178 __asm__
volatile (
"csrrs %0, mip, %1\n"
183#elif defined(CONFIG_XTENSA)
184static inline void trigger_irq(
int irq)
186 z_xt_set_intset(
BIT((
unsigned int)irq));
189#elif defined(CONFIG_SPARC)
190extern void z_sparc_enter_irq(
int);
192static inline void trigger_irq(
int irq)
194 z_sparc_enter_irq(irq);
197#elif defined(CONFIG_MIPS)
198extern void z_mips_enter_irq(
int);
200static inline void trigger_irq(
int irq)
202 z_mips_enter_irq(irq);
205#elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM)
207extern void z_vim_arm_enter_irq(
int);
209static inline void trigger_irq(
int irq)
211 z_vim_arm_enter_irq(irq);
216#define NO_TRIGGER_FROM_SW
static ALWAYS_INLINE _cpu_t * arch_curr_cpu(void)
Definition arch_inlines.h:17
#define MPIDR_AFFLVL(mpidr, aff_level)
Definition cpu.h:101
#define GET_MPIDR()
Definition cpu.h:104
Driver for ARM Generic Interrupt Controller.
void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list)
raise SGI to target cores
#define GICD_SGIR
Definition gic.h:127
#define GICD_SGIR_SGIINTID(x)
Definition gic.h:207
#define GICD_SGIR_TGTFILT_REQONLY
Definition gic.h:199
static void arch_nop(void)
Do nothing and return.
#define BIT(n)
Unsigned integer with bit position n set (signed in assembly language).
Definition util_macro.h:44
#define zassert_true(cond,...)
Assert that cond is true.
Definition ztest_assert.h:275
static void x86_write_x2apic(unsigned int reg, uint64_t val)
Write 64-bit value to the local APIC in x2APIC mode.
Definition loapic.h:118
#define LOAPIC_SELF_IPI
Definition loapic.h:42
void posix_sw_set_pending_IRQ(unsigned int IRQn)
static void printk(const char *fmt,...)
Print kernel debugging message.
Definition printk.h:51
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
Definition sys-io-common.h:70