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mii.h
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/*
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* Copyright (c) 2016 Piotr Mienkowski
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_NET_MII_H_
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#define ZEPHYR_INCLUDE_NET_MII_H_
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/* MII management registers */
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#define MII_BMCR 0x0
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#define MII_BMSR 0x1
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#define MII_PHYID1R 0x2
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#define MII_PHYID2R 0x3
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#define MII_ANAR 0x4
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#define MII_ANLPAR 0x5
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#define MII_ANER 0x6
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#define MII_ANNPTR 0x7
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#define MII_ANLPRNPR 0x8
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#define MII_1KTCR 0x9
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#define MII_1KSTSR 0xa
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#define MII_MMD_ACR 0xd
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#define MII_MMD_AADR 0xe
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#define MII_ESTAT 0xf
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/* Basic Mode Control Register (BMCR) bit definitions */
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#define MII_BMCR_RESET (1 << 15)
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#define MII_BMCR_LOOPBACK (1 << 14)
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#define MII_BMCR_SPEED_LSB (1 << 13)
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#define MII_BMCR_AUTONEG_ENABLE (1 << 12)
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#define MII_BMCR_POWER_DOWN (1 << 11)
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#define MII_BMCR_ISOLATE (1 << 10)
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#define MII_BMCR_AUTONEG_RESTART (1 << 9)
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#define MII_BMCR_DUPLEX_MODE (1 << 8)
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#define MII_BMCR_SPEED_MSB (1 << 6)
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#define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13)
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#define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13)
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#define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13)
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#define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13)
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/* Basic Mode Status Register (BMSR) bit definitions */
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#define MII_BMSR_100BASE_T4 (1 << 15)
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#define MII_BMSR_100BASE_X_FULL (1 << 14)
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#define MII_BMSR_100BASE_X_HALF (1 << 13)
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#define MII_BMSR_10_FULL (1 << 12)
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#define MII_BMSR_10_HALF (1 << 11)
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#define MII_BMSR_100BASE_T2_FULL (1 << 10)
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#define MII_BMSR_100BASE_T2_HALF (1 << 9)
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#define MII_BMSR_EXTEND_STATUS (1 << 8)
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#define MII_BMSR_MF_PREAMB_SUPPR (1 << 6)
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#define MII_BMSR_AUTONEG_COMPLETE (1 << 5)
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#define MII_BMSR_REMOTE_FAULT (1 << 4)
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#define MII_BMSR_AUTONEG_ABILITY (1 << 3)
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#define MII_BMSR_LINK_STATUS (1 << 2)
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#define MII_BMSR_JABBER_DETECT (1 << 1)
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#define MII_BMSR_EXTEND_CAPAB (1 << 0)
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/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
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/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
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#define MII_ADVERTISE_NEXT_PAGE (1 << 15)
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#define MII_ADVERTISE_LPACK (1 << 14)
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#define MII_ADVERTISE_REMOTE_FAULT (1 << 13)
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#define MII_ADVERTISE_ASYM_PAUSE (1 << 11)
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#define MII_ADVERTISE_PAUSE (1 << 10)
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#define MII_ADVERTISE_100BASE_T4 (1 << 9)
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#define MII_ADVERTISE_100_FULL (1 << 8)
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#define MII_ADVERTISE_100_HALF (1 << 7)
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#define MII_ADVERTISE_10_FULL (1 << 6)
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#define MII_ADVERTISE_10_HALF (1 << 5)
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#define MII_ADVERTISE_SEL_MASK (0x1F << 0)
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#define MII_ADVERTISE_SEL_IEEE_802_3 0x01
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/* 1000BASE-T Control Register bit definitions */
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#define MII_ADVERTISE_1000_FULL (1 << 9)
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#define MII_ADVERTISE_1000_HALF (1 << 8)
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#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
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MII_ADVERTISE_100_HALF | MII_ADVERTISE_100_FULL |\
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MII_ADVERTISE_SEL_IEEE_802_3)
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/* Extended Status Register bit definitions */
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#define MII_ESTAT_1000BASE_X_FULL (1 << 15)
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#define MII_ESTAT_1000BASE_X_HALF (1 << 14)
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#define MII_ESTAT_1000BASE_T_FULL (1 << 13)
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#define MII_ESTAT_1000BASE_T_HALF (1 << 12)
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/* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */
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#define MII_MMD_ACR_DEVAD_MASK (0x1F << 0)
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#define MII_MMD_ACR_ADDR (0x00 << 14)
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#define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14)
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#define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14)
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#define MII_MMD_ACR_DATA_W_POS_INC (0x11 << 14)
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#endif
/* ZEPHYR_INCLUDE_NET_MII_H_ */
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mii.h
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