Zephyr API Documentation 3.7.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
mdio.h
Go to the documentation of this file.
1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
12#ifndef ZEPHYR_INCLUDE_NET_MDIO_H_
13#define ZEPHYR_INCLUDE_NET_MDIO_H_
14
24#ifdef __cplusplus
25extern "C" {
26#endif
27
48
49/* MDIO Manageable Device addresses */
51#define MDIO_MMD_PMAPMD 0x01U
53#define MDIO_MMD_WIS 0x02U
55#define MDIO_MMD_PCS 0x03U
57#define MDIO_MMD_PHYXS 0x04U
59#define MDIO_MMD_DTEXS 0x05U
61#define MDIO_MMD_TC 0x06U
63#define MDIO_MMD_AN 0x07U
65#define MDIO_MMD_SEPARATED_PMA1 0x08U
67#define MDIO_MMD_SEPARATED_PMA2 0x09U
69#define MDIO_MMD_SEPARATED_PMA3 0x0AU
71#define MDIO_MMD_SEPARATED_PMA4 0x0BU
73#define MDIO_MMD_C22EXT 0x1DU
75#define MDIO_MMD_VENDOR_SPECIFIC1 0x1EU
77#define MDIO_MMD_VENDOR_SPECIFIC2 0x1FU
78
79/* MDIO generic registers */
81#define MDIO_CTRL1 0x0000U
83#define MDIO_STAT1 0x0001U
85#define MDIO_DEVID1 0x0002U
87#define MDIO_DEVID2 0x0003U
89#define MDIO_SPEED 0x0004U
91#define MDIO_DEVS1 0x0005U
93#define MDIO_DEVS2 0x0006U
95#define MDIO_CTRL2 0x0007U
97#define MDIO_STAT2 0x0008U
99#define MDIO_PKGID1 0x000EU
101#define MDIO_PKGID2 0x000FU
102/* PCS Register: EEE capability Register */
103#define MDIO_PCS_EEE_CAP 0x0014U
104/* Auto-negotiation Register: EEE advertisement Register */
105#define MDIO_AN_EEE_ADV 0x003CU
106
107
108/* BASE-T1 registers */
110#define MDIO_AN_T1_CTRL 0x0200U
112#define MDIO_AN_T1_STAT 0x0201U
114#define MDIO_AN_T1_ADV_L 0x0202U
116#define MDIO_AN_T1_ADV_M 0x0203U
118#define MDIO_AN_T1_ADV_H 0x0204U
120#define MDIO_PMA_PMD_BT1_CTRL 0x0834U
121
122/* BASE-T1 Auto-negotiation Control register */
124#define MDIO_AN_T1_CTRL_RESTART BIT(9)
126#define MDIO_AN_T1_CTRL_EN BIT(12)
127
128/* BASE-T1 Auto-negotiation Status register */
130#define MDIO_AN_T1_STAT_LINK_STATUS BIT(2)
132#define MDIO_AN_T1_STAT_ABLE BIT(3)
134#define MDIO_AN_T1_STAT_REMOTE_FAULT BIT(4)
136#define MDIO_AN_T1_STAT_COMPLETE BIT(5)
138#define MDIO_AN_T1_STAT_PAGE_RX BIT(6)
139
140/* BASE-T1 Auto-negotiation Advertisement register [15:0] */
142#define MDIO_AN_T1_ADV_L_PAUSE_CAP BIT(10)
144#define MDIO_AN_T1_ADV_L_PAUSE_ASYM BIT(11)
146#define MDIO_AN_T1_ADV_L_FORCE_MS BIT(12)
148#define MDIO_AN_T1_ADV_L_REMOTE_FAULT BIT(13)
150#define MDIO_AN_T1_ADV_L_ACK BIT(14)
152#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ BIT(15)
153
154/* BASE-T1 Auto-negotiation Advertisement register [31:16] */
156#define MDIO_AN_T1_ADV_M_B10L BIT(14)
158#define MDIO_AN_T1_ADV_M_MST BIT(4)
159
160/* BASE-T1 Auto-negotiation Advertisement register [47:32] */
162#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ BIT(12)
164#define MDIO_AN_T1_ADV_H_10L_TX_HI BIT(13)
165
166/* BASE-T1 PMA/PMD control register */
168#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST BIT(14)
169
170
171/* 10BASE-T1L registers */
173#define MDIO_PMA_B10L_CTRL 0x08F6U
175#define MDIO_PMA_B10L_STAT 0x08F7U
177#define MDIO_PMA_B10L_LINK_STAT 0x8302U
179#define MDIO_PCS_B10L_CTRL 0x08E6U
181#define MDIO_PCS_B10L_STAT 0x08E7U
182
183/* 10BASE-T1L PMA control register */
185#define MDIO_PMA_B10L_CTRL_TX_DIS_MODE_EN BIT(14)
187#define MDIO_PMA_B10L_CTRL_TX_LVL_HI BIT(12)
189#define MDIO_PMA_B10L_CTRL_EEE BIT(10)
191#define MDIO_PMA_B10L_CTRL_LB_PMA_LOC_EN BIT(0)
192
193/* 10BASE-T1L PMA status register */
195#define MDIO_PMA_B10L_STAT_LINK BIT(0)
197#define MDIO_PMA_B10L_STAT_FAULT BIT(1)
199#define MDIO_PMA_B10L_STAT_POLARITY BIT(2)
201#define MDIO_PMA_B10L_STAT_RECV_FAULT BIT(9)
203#define MDIO_PMA_B10L_STAT_EEE BIT(10)
205#define MDIO_PMA_B10L_STAT_LOW_POWER BIT(11)
207#define MDIO_PMA_B10L_STAT_2V4_ABLE BIT(12)
209#define MDIO_PMA_B10L_STAT_LB_ABLE BIT(13)
210
211/* 10BASE-T1L PMA link status*/
213#define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK_LL BIT(9)
215#define MDIO_PMA_B10L_LINK_STAT_REM_RCVR_STAT_OK BIT(8)
217#define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK_LL BIT(7)
219#define MDIO_PMA_B10L_LINK_STAT_LOC_RCVR_STAT_OK BIT(6)
221#define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK_LL BIT(5)
223#define MDIO_PMA_B10L_LINK_STAT_DSCR_STAT_OK BIT(4)
225#define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK_LL BIT(1)
227#define MDIO_PMA_B10L_LINK_STAT_LINK_STAT_OK BIT(0)
228
229/* 10BASE-T1L PCS control */
231#define MDIO_PCS_B10L_CTRL_LB_PCS_EN BIT(14)
232
233/* 10BASE-T1L PCS status */
235#define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL BIT(2)
236
237/* Auto-negotiation Register: EEE advertisement Register */
239#define MDIO_AN_EEE_ADV_1000T BIT(2)
241#define MDIO_AN_EEE_ADV_100TX BIT(1)
242
243#ifdef __cplusplus
244}
245#endif
246
251#endif /* ZEPHYR_INCLUDE_NET_MDIO_H_ */
mdio_opcode
MDIO transaction operation code.
Definition mdio.h:29
@ MDIO_OP_C45_READ
IEEE 802.3 45.3.4 read operation.
Definition mdio.h:46
@ MDIO_OP_C22_WRITE
IEEE 802.3 22.2.4.5.4 write operation.
Definition mdio.h:31
@ MDIO_OP_C22_READ
IEEE 802.3 22.2.4.5.4 read operation.
Definition mdio.h:34
@ MDIO_OP_C45_READ_INC
IEEE 802.3 45.3.4 post-read-increment-address operation.
Definition mdio.h:43
@ MDIO_OP_C45_ADDRESS
IEEE 802.3 45.3.4 address operation.
Definition mdio.h:37
@ MDIO_OP_C45_WRITE
IEEE 802.3 45.3.4 write operation.
Definition mdio.h:40