sd_spec.h

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/*
 * Copyright 2022-2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
/*
 * SD card specification
 */
 
#ifndef ZEPHYR_SUBSYS_SD_SPEC_H_
#define ZEPHYR_SUBSYS_SD_SPEC_H_
 
#include <stdint.h>
#include <zephyr/sys/util.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
enum sd_opcode {
        SD_GO_IDLE_STATE = 0,
        MMC_SEND_OP_COND = 1,
        SD_ALL_SEND_CID = 2,
        SD_SEND_RELATIVE_ADDR = 3,
        MMC_SEND_RELATIVE_ADDR = 3,
        SDIO_SEND_OP_COND = 5, /* SDIO cards only */
        SD_SWITCH = 6,
        SD_SELECT_CARD = 7,
        SD_SEND_IF_COND = 8,
        MMC_SEND_EXT_CSD = 8,
        SD_SEND_CSD = 9,
        SD_SEND_CID = 10,
        SD_VOL_SWITCH = 11,
        SD_STOP_TRANSMISSION = 12,
        SD_SEND_STATUS = 13,
        MMC_CHECK_BUS_TEST = 14,
        SD_GO_INACTIVE_STATE = 15,
        SD_SET_BLOCK_SIZE = 16,
        SD_READ_SINGLE_BLOCK = 17,
        SD_READ_MULTIPLE_BLOCK = 18,
        SD_SEND_TUNING_BLOCK = 19,
        MMC_SEND_BUS_TEST = 19,
        MMC_SEND_TUNING_BLOCK = 21,
        SD_SET_BLOCK_COUNT = 23,
        SD_WRITE_SINGLE_BLOCK = 24,
        SD_WRITE_MULTIPLE_BLOCK = 25,
        SD_ERASE_BLOCK_START = 32,
        SD_ERASE_BLOCK_END = 33,
        SD_ERASE_BLOCK_OPERATION = 38,
        SDIO_RW_DIRECT = 52,
        SDIO_RW_EXTENDED = 53,
        SD_APP_CMD = 55,
        SD_SPI_READ_OCR = 58, /* SPI mode only */
        SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */
};
 
enum sd_app_cmd {
        SD_APP_SET_BUS_WIDTH = 6,
        SD_APP_SEND_STATUS = 13,
        SD_APP_SEND_NUM_WRITTEN_BLK = 22,
        SD_APP_SET_WRITE_BLK_ERASE_CNT = 23,
        SD_APP_SEND_OP_COND = 41,
        SD_APP_CLEAR_CARD_DETECT = 42,
        SD_APP_SEND_SCR = 51,
};
 
enum sd_r1_status {
        /* Bits 0-2 reserved */
        SD_R1_AUTH_ERR = BIT(3),
        /* Bit 4 reserved for SDIO */
        SD_R1_APP_CMD = BIT(5),
        SD_R1_FX_EVENT = BIT(6),
        /* Bit 7 reserved */
        SD_R1_RDY_DATA = BIT(8),
        SD_R1_CUR_STATE = (0xFU << 9),
        SD_R1_ERASE_RESET = BIT(13),
        SD_R1_ECC_DISABLED = BIT(14),
        SD_R1_ERASE_SKIP = BIT(15),
        SD_R1_CSD_OVERWRITE = BIT(16),
        /* Bits 17-18 reserved */
        SD_R1_ERR = BIT(19),
        SD_R1_CC_ERR = BIT(20),
        SD_R1_ECC_FAIL = BIT(21),
        SD_R1_ILLEGAL_CMD = BIT(22),
        SD_R1_CRC_ERR = BIT(23),
        SD_R1_UNLOCK_FAIL = BIT(24),
        SD_R1_CARD_LOCKED = BIT(25),
        SD_R1_WP_VIOLATION = BIT(26),
        SD_R1_ERASE_PARAM = BIT(27),
        SD_R1_ERASE_SEQ_ERR = BIT(28),
        SD_R1_BLOCK_LEN_ERR = BIT(29),
        SD_R1_ADDR_ERR = BIT(30),
        SD_R1_OUT_OF_RANGE = BIT(31),
        SD_R1_ERR_FLAGS = (SD_R1_AUTH_ERR |
                        SD_R1_ERASE_SKIP |
                        SD_R1_CSD_OVERWRITE |
                        SD_R1_ERR |
                        SD_R1_CC_ERR |
                        SD_R1_ECC_FAIL |
                        SD_R1_ILLEGAL_CMD |
                        SD_R1_CRC_ERR |
                        SD_R1_UNLOCK_FAIL |
                        SD_R1_WP_VIOLATION |
                        SD_R1_ERASE_PARAM |
                        SD_R1_ERASE_SEQ_ERR |
                        SD_R1_BLOCK_LEN_ERR |
                        SD_R1_ADDR_ERR |
                        SD_R1_OUT_OF_RANGE),
        SD_R1ERR_NONE = 0,
};
 
#define SD_R1_CURRENT_STATE(x) (((x) & SD_R1_CUR_STATE) >> 9U)
 
enum sd_r1_current_state {
        SDMMC_R1_IDLE = 0U,
        SDMMC_R1_READY = 1U,
        SDMMC_R1_IDENTIFY = 2U,
        SDMMC_R1_STANDBY = 3U,
        SDMMC_R1_TRANSFER = 4U,
        SDMMC_R1_SEND_DATA = 5U,
        SDMMC_R1_RECIVE_DATA = 6U,
        SDMMC_R1_PROGRAM = 7U,
        SDMMC_R1_DISCONNECT = 8U,
};
 
enum sd_spi_r1_error_flag {
        SD_SPI_R1PARAMETER_ERR = BIT(6),
        SD_SPI_R1ADDRESS_ERR = BIT(5),
        SD_SPI_R1ERASE_SEQ_ERR = BIT(4),
        SD_SPI_R1CMD_CRC_ERR = BIT(3),
        SD_SPI_R1ILLEGAL_CMD_ERR = BIT(2),
        SD_SPI_R1ERASE_RESET = BIT(1),
        SD_SPI_R1IDLE_STATE = BIT(0),
};
 
enum sd_spi_r2_status {
        SDHC_SPI_R2_CARD_LOCKED = BIT(8),
        SDHC_SPI_R2_UNLOCK_FAIL = BIT(9),
        SDHC_SPI_R2_ERR = BIT(10),
        SDHC_SPI_R2_CC_ERR = BIT(11),
        SDHC_SPI_R2_ECC_FAIL = BIT(12),
        SDHC_SPI_R2_WP_VIOLATION = BIT(13),
        SDHC_SPI_R2_ERASE_PARAM = BIT(14),
        SDHC_SPI_R2_OUT_OF_RANGE = BIT(15),
};
 
/* Byte length of SD SPI mode command */
#define SD_SPI_CMD_SIZE 6
#define SD_SPI_CMD_BODY_SIZE (SD_SPI_CMD_SIZE - 1)
/* Byte length of CRC16 appended to data blocks in SPI mode */
#define SD_SPI_CRC16_SIZE 2
 
/* SPI Command flags */
#define SD_SPI_START 0x80
#define SD_SPI_TX 0x40
#define SD_SPI_CMD 0x3F
 
/* SPI Data block tokens */
#define SD_SPI_TOKEN_SINGLE 0xFE
#define SD_SPI_TOKEN_MULTI_WRITE 0xFC
#define SD_SPI_TOKEN_STOP_TRAN 0xFD
 
/* SPI Data block responses */
#define SD_SPI_RESPONSE_ACCEPTED 0x05
#define SD_SPI_RESPONSE_CRC_ERR 0x0B
#define SD_SPI_RESPONSE_WRITE_ERR 0x0C
 
/* Masks used in SD interface condition query (CMD8) */
#define SD_IF_COND_VHS_MASK (0x0F << 8)
#define SD_IF_COND_VHS_3V3 BIT(8)
#define SD_IF_COND_CHECK 0xAA
 
enum sd_rsp_type {
        /* Native response types (lower 4 bits) */
        SD_RSP_TYPE_NONE = 0U,
        SD_RSP_TYPE_R1 = 1U,
        SD_RSP_TYPE_R1b = 2U,
        SD_RSP_TYPE_R2 = 3U,
        SD_RSP_TYPE_R3 = 4U,
        SD_RSP_TYPE_R4 = 5U,
        SD_RSP_TYPE_R5 = 6U,
        SD_RSP_TYPE_R5b = 7U,
        SD_RSP_TYPE_R6 = 8U,
        SD_RSP_TYPE_R7 = 9U,
        /* SPI response types (bits [7:4]) */
        SD_SPI_RSP_TYPE_R1 = (1U << 4),
        SD_SPI_RSP_TYPE_R1b = (2U << 4),
        SD_SPI_RSP_TYPE_R2 = (3U << 4),
        SD_SPI_RSP_TYPE_R3 = (4U << 4),
        SD_SPI_RSP_TYPE_R4 = (5U << 4),
        SD_SPI_RSP_TYPE_R5 = (6U << 4),
        SD_SPI_RSP_TYPE_R7 = (7U << 4),
};
 
enum sd_support_flag {
        SD_HIGH_CAPACITY_FLAG = BIT(1),
        SD_4BITS_WIDTH = BIT(2),
        SD_SDHC_FLAG = BIT(3),
        SD_SDXC_FLAG = BIT(4),
        SD_1800MV_FLAG = BIT(5),
        SD_3000MV_FLAG = BIT(6),
        SD_CMD23_FLAG = BIT(7),
        SD_SPEED_CLASS_CONTROL_FLAG = BIT(8),
        SD_MEM_PRESENT_FLAG = BIT(9),
};
 
 
enum sd_ocr_flag {
        SD_OCR_PWR_BUSY_FLAG = BIT(31),
        SD_OCR_HOST_CAP_FLAG = BIT(30),
        SD_OCR_CARD_CAP_FLAG = SD_OCR_HOST_CAP_FLAG,
        SD_OCR_SWITCH_18_REQ_FLAG = BIT(24),
        SD_OCR_SWITCH_18_ACCEPT_FLAG = SD_OCR_SWITCH_18_REQ_FLAG,
        SD_OCR_VDD27_28FLAG = BIT(15),
        SD_OCR_VDD28_29FLAG = BIT(16),
        SD_OCR_VDD29_30FLAG = BIT(17),
        SD_OCR_VDD30_31FLAG = BIT(18),
        SD_OCR_VDD31_32FLAG = BIT(19),
        SD_OCR_VDD32_33FLAG = BIT(20),
        SD_OCR_VDD33_34FLAG = BIT(21),
        SD_OCR_VDD34_35FLAG = BIT(22),
        SD_OCR_VDD35_36FLAG = BIT(23),
};
 
enum mmc_ocr_flag {
        MMC_OCR_VDD170_195FLAG = BIT(7),
        MMC_OCR_VDD20_26FLAG = 0x7F << 8,
        MMC_OCR_VDD27_36FLAG = 0x1FF << 15,
        MMC_OCR_SECTOR_MODE = BIT(30),
        MMC_OCR_PWR_BUSY_FLAG = BIT(31)
};
 
#define SDIO_OCR_IO_NUMBER_SHIFT 28
/* Lower 24 bits hold SDIO I/O OCR */
#define SDIO_IO_OCR_MASK 0xFFFFFF
 
enum sdio_ocr_flag {
        SDIO_OCR_IO_READY_FLAG = BIT(31),
        SDIO_OCR_IO_NUMBER = (7U << 28U), 
        SDIO_OCR_MEM_PRESENT_FLAG = BIT(27), 
        SDIO_OCR_180_VOL_FLAG = BIT(24),        
        SDIO_OCR_VDD20_21FLAG = BIT(8),  
        SDIO_OCR_VDD21_22FLAG = BIT(9),  
        SDIO_OCR_VDD22_23FLAG = BIT(10), 
        SDIO_OCR_VDD23_24FLAG = BIT(11), 
        SDIO_OCR_VDD24_25FLAG = BIT(12), 
        SDIO_OCR_VDD25_26FLAG = BIT(13), 
        SDIO_OCR_VDD26_27FLAG = BIT(14), 
        SDIO_OCR_VDD27_28FLAG = BIT(15), 
        SDIO_OCR_VDD28_29FLAG = BIT(16), 
        SDIO_OCR_VDD29_30FLAG = BIT(17), 
        SDIO_OCR_VDD30_31FLAG = BIT(18), 
        SDIO_OCR_VDD31_32FLAG = BIT(19), 
        SDIO_OCR_VDD32_33FLAG = BIT(20), 
        SDIO_OCR_VDD33_34FLAG = BIT(21), 
        SDIO_OCR_VDD34_35FLAG = BIT(22), 
        SDIO_OCR_VDD35_36FLAG = BIT(23), 
};
 
 
enum sd_switch_arg {
        SD_SWITCH_CHECK = 0U,
        SD_SWITCH_SET = 1U,
};
 
enum sd_group_num {
        SD_GRP_TIMING_MODE = 0U,
        SD_GRP_CMD_SYS_MODE = 1U,
        SD_GRP_DRIVER_STRENGTH_MODE = 2U,
        SD_GRP_CURRENT_LIMIT_MODE = 3U,
};
 
/* Maximum data rate possible for SD high speed cards */
enum hs_max_data_rate {
        HS_UNSUPPORTED = 0,
        HS_MAX_DTR = MHZ(50),
};
 
/* Maximum data rate possible for SD uhs cards */
enum uhs_max_data_rate {
        UHS_UNSUPPORTED = 0,
        UHS_SDR12_MAX_DTR = MHZ(25),
        UHS_SDR25_MAX_DTR = MHZ(50),
        UHS_SDR50_MAX_DTR = MHZ(100),
        UHS_SDR104_MAX_DTR = MHZ(208),
        UHS_DDR50_MAX_DTR = MHZ(50),
};
 
enum sd_bus_speed {
        UHS_SDR12_BUS_SPEED = BIT(0),
        DEFAULT_BUS_SPEED = BIT(0),
        HIGH_SPEED_BUS_SPEED = BIT(1),
        UHS_SDR25_BUS_SPEED = BIT(1),
        UHS_SDR50_BUS_SPEED = BIT(2),
        UHS_SDR104_BUS_SPEED = BIT(3),
        UHS_DDR50_BUS_SPEED = BIT(4),
};
 
enum sd_timing_mode {
        SD_TIMING_DEFAULT = 0U,
        SD_TIMING_SDR12 = 0U,
        SD_TIMING_HIGH_SPEED = 1U,
        SD_TIMING_SDR25 = 1U,
        SD_TIMING_SDR50 = 2U,
        SD_TIMING_SDR104 = 3U,
        SD_TIMING_DDR50 = 4U,
};
 
enum sdhc_clock_speed {
        SDMMC_CLOCK_400KHZ = KHZ(400),
        SD_CLOCK_25MHZ = MHZ(25),
        SD_CLOCK_50MHZ = MHZ(50),
        SD_CLOCK_100MHZ = MHZ(100),
        SD_CLOCK_208MHZ = MHZ(208),
        MMC_CLOCK_26MHZ = MHZ(26),
        MMC_CLOCK_52MHZ = MHZ(52),
        MMC_CLOCK_DDR52 = MHZ(52),
        MMC_CLOCK_HS200 = MHZ(200),
        MMC_CLOCK_HS400 = MHZ(200), /* Same clock freq as HS200, just DDR */
};
 
enum sd_current_setting {
        SD_SET_CURRENT_200MA = 0,
        SD_SET_CURRENT_400MA = 1,
        SD_SET_CURRENT_600MA = 2,
        SD_SET_CURRENT_800MA = 3,
};
 
enum sd_current_limit {
        SD_MAX_CURRENT_200MA = BIT(0),
        SD_MAX_CURRENT_400MA = BIT(1),
        SD_MAX_CURRENT_600MA = BIT(2),
        SD_MAX_CURRENT_800MA = BIT(3),
};
 
enum sd_driver_type {
        SD_DRIVER_TYPE_B = 0x1,
        SD_DRIVER_TYPE_A = 0x2,
        SD_DRIVER_TYPE_C = 0x4,
        SD_DRIVER_TYPE_D = 0x8,
};
 
enum sd_driver_strength {
        SD_DRV_STRENGTH_TYPEB = 0U,
        SD_DRV_STRENGTH_TYPEA = 1U,
        SD_DRV_STRENGTH_TYPEC = 2U,
        SD_DRV_STRENGTH_TYPED = 3U,
};
 
struct sd_switch_caps {
        enum hs_max_data_rate hs_max_dtr;
        enum uhs_max_data_rate uhs_max_dtr;
        enum sd_bus_speed bus_speed;
        enum sd_driver_type sd_drv_type;
        enum sd_current_limit sd_current_limit;
};
 
 
#define SD_PRODUCT_NAME_BYTES 5
 
struct sd_cid {
        uint8_t manufacturer;
        uint16_t application;
        uint8_t name[SD_PRODUCT_NAME_BYTES];
        uint8_t version;
        uint32_t ser_num;
        uint16_t date;
};
 
struct sd_csd {
        uint8_t csd_structure;
        uint8_t read_time1;
        uint8_t read_time2;
        uint8_t xfer_rate;
        uint16_t cmd_class;
        uint8_t read_blk_len;
        uint16_t flags;
        uint32_t device_size;
        uint8_t read_current_min;
        uint8_t read_current_max;
        uint8_t write_current_min;
        uint8_t write_current_max;
        uint8_t dev_size_mul;
        uint8_t erase_size;
        uint8_t write_prtect_size;
        uint8_t write_speed_factor;
        uint8_t write_blk_len;
        uint8_t file_fmt;
};
 
enum mmc_csd_freq {
        MMC_MAXFREQ_100KHZ = 0U << 0U,
        MMC_MAXFREQ_1MHZ = 1U << 0U,
        MMC_MAXFREQ_10MHZ = 2U << 0U,
        MMC_MAXFREQ_100MHZ = 3U << 0U,
        MMC_MAXFREQ_MULT_10 = 1U << 3U,
        MMC_MAXFREQ_MULT_12 = 2U << 3U,
        MMC_MAXFREQ_MULT_13 = 3U << 3U,
        MMC_MAXFREQ_MULT_15 = 4U << 3U,
        MMC_MAXFREQ_MULT_20 = 5U << 3U,
        MMC_MAXFREQ_MULT_26 = 6U << 3U,
        MMC_MAXFREQ_MULT_30 = 7U << 3U,
        MMC_MAXFREQ_MULT_35 = 8U << 3U,
        MMC_MAXFREQ_MULT_40 = 9U << 3U,
        MMC_MAXFREQ_MULT_45 = 0xAU << 3U,
        MMC_MAXFREQ_MULT_52 = 0xBU << 3U,
        MMC_MAXFREQ_MULT_55 = 0xCU << 3U,
        MMC_MAXFREQ_MULT_60 = 0xDU << 3U,
        MMC_MAXFREQ_MULT_70 = 0xEU << 3U,
        MMC_MAXFREQ_MULT_80 = 0xFU << 3u
};
 
enum mmc_timing_mode {
        MMC_LEGACY_TIMING = 0U,
        MMC_HS_TIMING = 1U,
        MMC_HS200_TIMING = 2U,
        MMC_HS400_TIMING = 3U
};
 
enum mmc_driver_strengths {
        mmc_driv_type0 = 0U,
        mmc_driv_type1 = 1U,
        mmc_driv_type2 = 2U,
        mmc_driv_type3 = 3U,
        mmc_driv_type4 = 4U
};
 
 
struct mmc_device_type {
        bool MMC_HS400_DDR_1200MV;
        bool MMC_HS400_DDR_1800MV;
        bool MMC_HS200_SDR_1200MV;
        bool MMC_HS200_SDR_1800MV;
        bool MMC_HS_DDR_1200MV;
        bool MMC_HS_DDR_1800MV;
        bool MMC_HS_52_DV;
        bool MMC_HS_26_DV;
};
 
enum mmc_ext_csd_rev {
        MMC_5_1 = 8U,
        MMC_5_0 = 7U,
        MMC_4_5 = 6U,
        MMC_4_4 = 5U,
        MMC_4_3 = 3U,
        MMC_4_2 = 2U,
        MMC_4_1 = 1U,
        MMC_4_0 = 0U
};
 
struct mmc_ext_csd {
        uint32_t sec_count;
        uint8_t bus_width;
        enum mmc_timing_mode hs_timing;
        struct mmc_device_type device_type;
        enum mmc_ext_csd_rev rev;
        uint8_t power_class;
        uint8_t mmc_driver_strengths;
        uint8_t pwr_class_200MHZ_VCCQ195;
        uint8_t pwr_class_HS400;
        uint32_t cache_size;
};
 
enum sd_csd_flag {
        SD_CSD_READ_BLK_PARTIAL_FLAG = BIT(0),
        SD_CSD_WRITE_BLK_MISALIGN_FLAG = BIT(1),
        SD_CSD_READ_BLK_MISALIGN_FLAG = BIT(2),
        SD_CSD_DSR_IMPLEMENTED_FLAG = BIT(3),
        SD_CSD_ERASE_BLK_EN_FLAG = BIT(4),
        SD_CSD_WRITE_PROTECT_GRP_EN_FLAG = BIT(5),
        SD_CSD_WRITE_BLK_PARTIAL_FLAG = BIT(6),
        SD_CSD_FILE_FMT_GRP_FLAG = BIT(7),
        SD_CSD_COPY_FLAG = BIT(8),
        SD_CSD_PERMANENT_WRITE_PROTECT_FLAG = BIT(9),
        SD_CSD_TMP_WRITE_PROTECT_FLAG = BIT(10),
};
 
struct sd_scr {
        uint8_t scr_structure;
        uint8_t sd_spec;
        uint16_t flags;
        uint8_t sd_sec;
        uint8_t sd_width;
        uint8_t sd_ext_sec;
        uint8_t cmd_support;
        uint32_t rsvd;
};
 
enum sd_scr_flag {
        SD_SCR_DATA_STATUS_AFTER_ERASE = BIT(0),
        SD_SCR_SPEC3 = BIT(1),
};
 
enum sd_spec_version {
        SD_SPEC_VER1_0 = BIT(0),
        SD_SPEC_VER1_1 = BIT(1),
        SD_SPEC_VER2_0 = BIT(2),
        SD_SPEC_VER3_0 = BIT(3),
};
 
 
#define SDMMC_DEFAULT_BLOCK_SIZE 512
#define MMC_EXT_CSD_BYTES 512
enum sdio_func_num {
        SDIO_FUNC_NUM_0 = 0,
        SDIO_FUNC_NUM_1 = 1,
        SDIO_FUNC_NUM_2 = 2,
        SDIO_FUNC_NUM_3 = 3,
        SDIO_FUNC_NUM_4 = 4,
        SDIO_FUNC_NUM_5 = 5,
        SDIO_FUNC_NUM_6 = 6,
        SDIO_FUNC_NUM_7 = 7,
        SDIO_FUNC_MEMORY = 8,
};
 
enum sdio_io_dir {
        SDIO_IO_READ = 0,
        SDIO_IO_WRITE = 1,
};
 
#define SDIO_CMD_ARG_RW_SHIFT 31                
#define SDIO_CMD_ARG_FUNC_NUM_SHIFT 28  
#define SDIO_DIRECT_CMD_ARG_RAW_SHIFT 27        
#define SDIO_CMD_ARG_REG_ADDR_SHIFT 9   
#define SDIO_CMD_ARG_REG_ADDR_MASK 0x1FFFF      
#define SDIO_DIRECT_CMD_DATA_MASK 0xFF  
#define SDIO_EXTEND_CMD_ARG_BLK_SHIFT 27        
#define SDIO_EXTEND_CMD_ARG_OP_CODE_SHIFT 26    
#define SDIO_CCCR_CCCR 0x00 
#define SDIO_CCCR_CCCR_REV_MASK 0x0F
#define SDIO_CCCR_CCCR_REV_SHIFT 0x0
#define SDIO_CCCR_CCCR_REV_1_00 0x0 
#define SDIO_CCCR_CCCR_REV_1_10 0x1 
#define SDIO_CCCR_CCCR_REV_2_00 0x2 
#define SDIO_CCCR_CCCR_REV_3_00 0x3 
#define SDIO_CCCR_SD 0x01 
#define SDIO_CCCR_SD_SPEC_MASK 0x0F
#define SDIO_CCCR_SD_SPEC_SHIFT 0x0
 
#define SDIO_CCCR_IO_EN 0x02 
#define SDIO_CCCR_IO_RD 0x03 
#define SDIO_CCCR_INT_EN 0x04 
#define SDIO_CCCR_INT_P 0x05 
#define SDIO_CCCR_ABORT 0x06 
#define SDIO_CCCR_BUS_IF 0x07 
#define SDIO_CCCR_BUS_IF_WIDTH_MASK 0x3 
#define SDIO_CCCR_BUS_IF_WIDTH_1_BIT 0x00 
#define SDIO_CCCR_BUS_IF_WIDTH_4_BIT 0x02 
#define SDIO_CCCR_BUS_IF_WIDTH_8_BIT 0x03 
#define SDIO_CCCR_CAPS 0x08 
#define SDIO_CCCR_CAPS_SDC BIT(0) 
#define SDIO_CCCR_CAPS_SMB BIT(1) 
#define SDIO_CCCR_CAPS_SRW BIT(2) 
#define SDIO_CCCR_CAPS_SBS BIT(3) 
#define SDIO_CCCR_CAPS_S4MI BIT(4) 
#define SDIO_CCCR_CAPS_E4MI BIT(5) 
#define SDIO_CCCR_CAPS_LSC BIT(6) 
#define SDIO_CCCR_CAPS_BLS BIT(7) 
#define SDIO_CCCR_CIS 0x09 
#define SDIO_CCCR_SPEED 0x13 
#define SDIO_CCCR_SPEED_SHS BIT(0) 
#define SDIO_CCCR_SPEED_MASK 0xE 
#define SDIO_CCCR_SPEED_SHIFT 0x1 
#define SDIO_CCCR_SPEED_SDR12 0x0 
#define SDIO_CCCR_SPEED_HS 0x1 
#define SDIO_CCCR_SPEED_SDR25 0x1 
#define SDIO_CCCR_SPEED_SDR50 0x2 
#define SDIO_CCCR_SPEED_SDR104 0x3 
#define SDIO_CCCR_SPEED_DDR50 0x4 
#define SDIO_CCCR_UHS 0x14 
#define SDIO_CCCR_UHS_SDR50 BIT(0) 
#define SDIO_CCCR_UHS_SDR104 BIT(1) 
#define SDIO_CCCR_UHS_DDR50 BIT(2) 
#define SDIO_CCCR_DRIVE_STRENGTH 0x15 
#define SDIO_CCCR_DRIVE_STRENGTH_A BIT(0) 
#define SDIO_CCCR_DRIVE_STRENGTH_C BIT(1) 
#define SDIO_CCCR_DRIVE_STRENGTH_D BIT(2) 
#define SDIO_FBR_BASE(n) ((n) * 0x100) 
#define SDIO_FBR_CIS 0x09 
#define SDIO_FBR_CSA 0x0C 
#define SDIO_FBR_BLK_SIZE 0x10 
#define SDIO_MAX_IO_NUMS 7 
#define SDIO_TPL_CODE_NULL 0x00 
#define SDIO_TPL_CODE_MANIFID 0x20 
#define SDIO_TPL_CODE_FUNCID 0x21 
#define SDIO_TPL_CODE_FUNCE 0x22 
#define SDIO_TPL_CODE_END 0xFF 
enum sdio_cccr_flags {
        SDIO_SUPPORT_HS = BIT(0),
        SDIO_SUPPORT_SDR50 = BIT(1),
        SDIO_SUPPORT_SDR104 = BIT(2),
        SDIO_SUPPORT_DDR50 = BIT(3),
        SDIO_SUPPORT_4BIT_LS_BUS = BIT(4),
        SDIO_SUPPORT_MULTIBLOCK = BIT(5),
};
 
struct sdio_cis {
        /* Manufacturer ID string tuple */
        uint16_t manf_id; 
        uint16_t manf_code; 
        /* Function identification tuple */
        uint8_t func_id; 
        /* Function extension table */
        uint16_t max_blk_size; 
        uint8_t max_speed; 
        uint16_t rdy_timeout; 
};
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_SUBSYS_SD_SPEC_H_ */