stm32c0_clock.h

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/*
 * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
 
#include "stm32_common_clocks.h"
 
#define STM32_CLOCK_BUS_IOP     0x034
#define STM32_CLOCK_BUS_AHB1    0x038
#define STM32_CLOCK_BUS_APB1    0x03c
#define STM32_CLOCK_BUS_APB1_2  0x040
 
#define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1_2
 
/* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
 
/* defined in stm32_common_clocks.h */
/* Low speed clocks defined in stm32_common_clocks.h */
#define STM32_SRC_HSI48         (STM32_SRC_LSI + 1)
#define STM32_SRC_HSE           (STM32_SRC_HSI48 + 1)
#define STM32_SRC_PCLK          (STM32_SRC_HSE + 1)
 
#define STM32_CLOCK_REG_MASK    0xFFU
#define STM32_CLOCK_REG_SHIFT   0U
#define STM32_CLOCK_SHIFT_MASK  0x1FU
#define STM32_CLOCK_SHIFT_SHIFT 8U
#define STM32_CLOCK_MASK_MASK   0x7U
#define STM32_CLOCK_MASK_SHIFT  13U
#define STM32_CLOCK_VAL_MASK    0x7U
#define STM32_CLOCK_VAL_SHIFT   16U
 
#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                       \
        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
 
#define CCIPR_REG               0x54
 
#define CSR1_REG                0x5C
 
#define CFGR1_REG               0x08
 
#define USART1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
#define I2C1_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
#define I2C2_I2S1_SEL(val)      STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
#define ADC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
#define RTC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)
 
#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
 
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_1   0
#define MCO_PRE_DIV_2   1
#define MCO_PRE_DIV_4   2
#define MCO_PRE_DIV_8   3
#define MCO_PRE_DIV_16  4
#define MCO_PRE_DIV_32  5
#define MCO_PRE_DIV_64  6
#define MCO_PRE_DIV_128 7
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */