apidoc/latest/stm32g0__clock_8h_source.html

/*

 * Copyright (c) 2022 Linaro Limited

 *

 * SPDX-License-Identifier: Apache-2.0

 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_

#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_


#include "stm32_common_clocks.h"


#define STM32_CLOCK_BUS_IOP     0x034

#define STM32_CLOCK_BUS_AHB1    0x038

#define STM32_CLOCK_BUS_APB1    0x03c

#define STM32_CLOCK_BUS_APB1_2  0x040


#define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_IOP

#define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1_2


/* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */


/* defined in stm32_common_clocks.h */

/* Low speed clocks defined in stm32_common_clocks.h */

#define STM32_SRC_HSI           (STM32_SRC_LSI + 1)

#define STM32_SRC_HSI48         (STM32_SRC_HSI + 1)

#define STM32_SRC_MSI           (STM32_SRC_HSI48 + 1)

#define STM32_SRC_HSE           (STM32_SRC_MSI + 1)

#define STM32_SRC_PCLK          (STM32_SRC_HSE + 1)

#define STM32_SRC_PLL_P         (STM32_SRC_PCLK + 1)

#define STM32_SRC_PLL_Q         (STM32_SRC_PLL_P + 1)

#define STM32_SRC_PLL_R         (STM32_SRC_PLL_Q + 1)


#define STM32_CLOCK_REG_MASK    0xFFU

#define STM32_CLOCK_REG_SHIFT   0U

#define STM32_CLOCK_SHIFT_MASK  0x1FU

#define STM32_CLOCK_SHIFT_SHIFT 8U

#define STM32_CLOCK_MASK_MASK   0x7U

#define STM32_CLOCK_MASK_SHIFT  13U

#define STM32_CLOCK_VAL_MASK    0x7U

#define STM32_CLOCK_VAL_SHIFT   16U


#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                       \

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \

         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \

         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \

         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))


#define CCIPR_REG               0x54

#define CCIPR2_REG              0x58


#define BDCR_REG                0x5C


#define USART1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)

#define USART2_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)

#define USART3_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)

#define CEC_SEL(val)            STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG)

#define LPUART2_SEL(val)        STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)

#define LPUART1_SEL(val)        STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)

#define I2C1_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)

#define I2C2_I2S1_SEL(val)      STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)

#define LPTIM1_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)

#define LPTIM2_SEL(val)         STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)

#define TIM1_SEL(val)           STM32_DOMAIN_CLOCK(val, 1, 22, CCIPR_REG)

#define TIM15_SEL(val)          STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG)

#define RNG_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)

#define ADC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)

#define I2S1_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)

#define I2S2_SEL(val)           STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR2_REG)

#define FDCAN_SEL(val)          STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR2_REG)

#define USB_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)

#define RTC_SEL(val)            STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)


#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */

stm32_common_clocks.h