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4.1.99
A Scalable Open Source RTOS
4.1.99
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stm32h7rs_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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/* RM0477 */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1)
/* HSI + HSIKERON */
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#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1)
/* CSI + CSIKERON */
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#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
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#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
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#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
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#define STM32_SRC_PLL1_S (STM32_SRC_PLL1_R + 1)
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#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_S + 1)
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#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
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#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
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#define STM32_SRC_PLL2_S (STM32_SRC_PLL2_R + 1)
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#define STM32_SRC_PLL2_T (STM32_SRC_PLL2_S + 1)
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#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_T + 1)
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#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
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#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
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#define STM32_SRC_PLL3_S (STM32_SRC_PLL3_R + 1)
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#define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1)
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#define STM32_CLOCK_BUS_AHB1 0x138
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#define STM32_CLOCK_BUS_AHB2 0x13C
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#define STM32_CLOCK_BUS_AHB3 0x158
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#define STM32_CLOCK_BUS_AHB4 0x140
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#define STM32_CLOCK_BUS_AHB5 0x134
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#define STM32_CLOCK_BUS_APB1 0x148
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#define STM32_CLOCK_BUS_APB1_2 0x14C
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#define STM32_CLOCK_BUS_APB2 0x150
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#define STM32_CLOCK_BUS_APB4 0x154
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#define STM32_CLOCK_BUS_APB5 0x144
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB5
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB3
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#define D1CCIPR_REG 0x4C
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#define D2CCIPR_REG 0x50
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#define D3CCIPR_REG 0x54
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#define D4CCIPR_REG 0x58
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#define BDCR_REG 0x70
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#define CFGR_REG 0x10
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/* TODO to be completed */
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#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG)
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#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG)
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#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
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#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG)
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#define OTGFS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG)
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#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG)
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#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
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#define USART234578_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIPR_REG)
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#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D2CCIPR_REG)
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#define I2C23_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIPR_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG)
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#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIPR_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIPR_REG)
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG)
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#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D3CCIPR_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, D3CCIPR_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D3CCIPR_REG)
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#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, D3CCIPR_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D4CCIPR_REG)
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#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D4CCIPR_REG)
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#define LPTIM23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, D4CCIPR_REG)
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#define LPTIM45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D4CCIPR_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 29, CFGR_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 25, CFGR_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 1
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#define MCO_PRE_DIV_2 2
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#define MCO_PRE_DIV_3 3
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#define MCO_PRE_DIV_4 4
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#define MCO_PRE_DIV_5 5
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#define MCO_PRE_DIV_6 6
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#define MCO_PRE_DIV_7 7
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#define MCO_PRE_DIV_8 8
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#define MCO_PRE_DIV_9 9
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#define MCO_PRE_DIV_10 10
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#define MCO_PRE_DIV_11 11
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#define MCO_PRE_DIV_12 12
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#define MCO_PRE_DIV_13 13
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#define MCO_PRE_DIV_14 14
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#define MCO_PRE_DIV_15 15
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */
stm32_common_clocks.h
zephyr
dt-bindings
clock
stm32h7rs_clock.h
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