DesignWare ARC nSIM and HAPS FPGA boards¶
This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in simulation with Designware ARC nSIM or run same images on FPGA prototyping platform HAPS. The platform includes the following features:
ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to here for a complete list of ARC processor families which currently supported
Virtual serial console (a standard
ARC processors are known for being highly customizable and some but not all of the configurations are currently supported in the Zephyr RTOS for ARC, again please refer to here for a complete list of supported features.
There are multiple supported sub-configurations for that platform. Some but not all of currently available configurations are listed below:
nsim_em- ARC EM core v4.0 with two register banks, FastIRQ’s, MPUv2, DSP options and XY-memory
nsim_em_em7d_v22- ARC EM core v3.0 with one register bank and FastIRQ’s
nsim_em_em11d- ARC EM core v4.0 with one register bank, no FastIRQ’s, MPUv2, DSP options and XY-memory
nsim_sem- ARC EM core v4.0 with secure features (thus “SEM”, i.e. Secure EM) and MPUv4
nsim_hs- ARCv2 HS core v2.1 with two register banks, FastIRQ’s and MPUv3
nsim_hs_smp- Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ’s and MPUv3
nsim_vpx5- ARCv2 VPX5 core, close to vpx5_integer_full template
nsim_hs5x- 32-bit ARCv3 HS core with rich set of options
nsim_hs6x- 64-bit ARCv3 HS core with rich set of options
nsim_hs5x_smp_12cores- SMP 12 cores 32-bit ARCv3 HS platform
nsim_hs6x_smp_12cores- SMP 12 cores 64-bit ARCv3 HS platform
It is recommended to look at precise description of a particular sub-configuration in either
.args files in boards/arc/nsim/support/ directory to understand
which options are configured and so will be used on invocation of the simulator.
In case of single-core configurations it would be
.props file which contains configuration
for nSIM simulator and
.args file which contains configuration for MetaWare debugger (MDB).
Note that these files contain identical HW configuration and meant to be used with the corresponding
.props file for nSIM simulator and
.args file for MDB (which internally uses nSIM for
If different behavior is observed during execution or debugging of a particular application
(especially after creation of a new board or modification of the existing one) make sure features
.args are semantically identical (unfortunately options of
nSIM & MDB don’t exactly match, so care should be taken).
For the multi-core configurations there is only
.args file as the multi-core configuration
can only be instantiated with help of MDB.
I.e. for the multi-core
nsim_hs5x_smp platform there is only
All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to represent any real system and so might be renamed, removed or modified at any point.
Programming and Debugging¶
Required Hardware and Software¶
Building & Running Sample Applications¶
Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however
there might be exceptions from that, especially for newly added targets. You can check supported
toolchains for the sub-configurations in the corresponding
I.e. for the
nsim_hs5x board we can check boards/arc/nsim/nsim_hs5x.yaml
The supported toolchains are listed in
toolchain: array in
.yaml file, where we can find:
zephyr - implies ARC GNU toolchain from Zephyr SDK. You can find more information about Zephyr SDK here.
cross-compile - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that some (especially new) sub-configurations may declare
cross-compiletoolchain support without
zephyrtoolchain support because corresponding target CPU support hasn’t been added to Zephyr SDK yet. You can find more information about its usage here: here.
arcmwdt - implies proprietary ARC MWDT toolchain. You can find more information about its usage here: here.
Note that even if both GNU and MWDT toolchain support is declared for the target some tests or samples can be only built with either GNU or MWDT toolchain due to some features limited to a particular toolchain.
Use this configuration to run basic Zephyr applications and kernel tests in nSIM, for example, with the Basic Synchronization sample:
# From the root of the zephyr repository west build -b nsim_em samples/synchronization west flash
This will build an image with the synchronization sample app, boot it using nSIM, and display the following console output:
*** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** thread_a: Hello World from cpu 0 on nsim! thread_b: Hello World from cpu 0 on nsim! thread_a: Hello World from cpu 0 on nsim! thread_b: Hello World from cpu 0 on nsim! thread_a: Hello World from cpu 0 on nsim!
To exit the simulator, use Ctrl+], then Ctrl+c
You can get more details about the building process by running build in verbose mode. It can be
done by passing
-v flag to the west:
west -v build -b nsim_hs samples/synchronization
You can run applications built for
nsim board not only on nSIM simulation itself, but also on
FPGA based HW platform HAPS. To run previously built application on HAPS do:
west flash --runner mdb-hw
To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself as well as flash proper built FPGA image (aka .bit-file). This instruction doesn’t cover those steps, so you need to follow HAPS manual.
Debugging with MDB¶
We strongly recommend to debug with MetaWare debugger (MDB) because it:
Supports wider range of ARC hardware features
Allows to debug both single-core and multi-core
Allows to debug on HAPS platform.
You can use the following command to start GUI debugging when running application on nSIM simulator (regardless if single- or multi-core configuration is used):
west debug --runner mdb-nsim
You can use the following command to start GUI debugging when running application on HAPS platform:
west debug --runner mdb-hw
west debug (as well as
west flash) is just a wrapper script and so it’s possible to
extract the exact commands which are called in it by running it in verbose mode. For that you
need to pass
-v flag to the wrapper. For example, if you run the following command:
west -v debug --runner mdb-nsim
it will produce the following output (the
nsim_hs5x_smp configuration was used for that
< *snip* > -- west debug: using runner mdb-nsim runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN
From that output it’s possible to extract MDB commands used for setting-up the GUI debugging session:
mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf mdb -multifiles=core1,core0 -OKN
Then it’s possible to use them directly or in some machinery if required.
It is strongly recommended to not rely on the mdb command line options listed above but extract it yourself for your configuration.
In case of execution or debugging with MDB on multi-core configuration on nSIM
west flash and
west debug wrappers it’s necessary to
NSIM_MULTICORE environment variable to
1. If you are using
west flash or
west debug it’s done automatically by wrappers.
NSIM_MULTICORE environment variable set to 1, MDB will simulate 2 separate
ARC cores which don’t share any memory regions with each other and so SMP-enabled code won’t
work as expected.
Debugging with GDB¶
Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone nSIM). However if it’s possible to launch application on multi-core nsim target that means you can simply debug with MDB debugger. It’s the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC GDB.
Currently debugging with GDB is not supported on HAPS platform.
west debug command won’t work for debugging applications using nsim boards
because both the nSIM simulator and the debugger (either GDB or MDB) use the same console for
input / output.
In case of GDB debugger it’s possible to use a separate terminal windows for GDB and nSIM to
avoid intermixing their output. For the MDB debugger simply use GUI mode.
After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB server and wait for a remote connection with following command:
west debugserver --runner arc-nsim
In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK:
for the ARCv2 targets you should use
for the ARCv3 targets you should use
This command loads the symbol table from the elf binary file, for example the
arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf
Now the debug environment has been set up, and it’s possible to debug the application with gdb commands.
Modifying the configuration¶
If modification of existing nsim configuration is required or even there’s a need in creation of a new one it’s required to maintain alignment between
Zephyr OS configuration
nSIM & MDB configuration
GNU & MWDT toolchain compiler options
.tcf configuration files are not supported by Zephyr directly. There are multiple
reasons for that.
.tcf perfectly suits building of bare-metal single-thread application -
in that case all the compiler options from
.tcf are passed to the compiler, so all the HW
features are used by the application and optimal code is being generated.
The situation is completely different when multi-thread feature-rich operation system is
considered. Of course it is still possible to build all the code with all the
.tcf - but that may be far from optimal solution. For example, such approach
require so save & restore full register context for all tasks (and sometimes even for
interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra
registers save and restore even if the most of the user and kernel tasks don’t actually use
DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros)
require us to maintain them separately from
Zephyr OS configuration¶
Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific mechanisms which are described in board porting guide.
It is advised to look for
<board_name>.yaml as an entry point for board configuration.
nSIM configuration is defined in props and args files.
Generally they are identical to the values from corresponding
.tcf configuration with few
The UART model is added (to both
Options to fine-tuned MDB behavior are added (to
.argsfiles only) to disable MDB profiling and fine-tune MDB behavior on multi-core systems.
GNU & MWDT toolchain compiler options¶
The hardware-specific compiler options are set in corresponding SoC cmake file. For
it is soc/arc/snps_nsim/CMakeLists.txt.
For the GNU toolchain the basic configuration is set via
-mcpu which is defined in generic code
and based on the selected CPU model via Kconfig. It still can be forcefully set to required value
on SoC level.
For the MWDT toolchain all hardware-specific compiler options are set directly in SoC
The non hardware-specific compiler options like optimizations, library selections, C / C++ language options are still set in Zephyr generic code. It could be observed by running build in verbose mode.