The i.MX RT1050 is a new processor family featuring NXP’s advanced implementation of the ARM Cortex-M7 Core. It provides high CPU performance and real-time response. The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio interface.
The following document refers to the discontinued MIMXRT1050-EVK board. For the MIMXRT1050-EVKB board, refer to Board Revisions section.
- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM)
- 256 KB SDRAM
- 64 Mbit QSPI Flash
- 512 Mbit Hyper Flash
- LCD connector
- Touch connector
- 10/100 Mbit/s Ethernet PHY
- USB 2.0 OTG connector
- USB 2.0 host connector
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- 5 V DC jack
- JTAG 20-pin connector
- OpenSDA with DAPLink
- FXOS8700CQ 6-axis e-compass
- CMOS camera sensor interface
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see these references:
- i.MX RT1050 Website
- i.MX RT1050 Datasheet
- i.MX RT1050 Reference Manual
- MIMXRT1050-EVK Website
- MIMXRT1050-EVK User Guide
- MIMXRT1050-EVK Schematics
The mimxrt1050_evk board configuration supports the following hardware features:
|NVIC||on-chip||nested vector interrupt controller|
|UART||on-chip||serial port-polling; serial port-interrupt|
The default configuration can be found in the defconfig file:
Other hardware features are not currently supported by the port.
Connections and IOs¶
The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
|GPIO_AD_B1_06||LPUART3_TX||UART BT HCI|
|GPIO_AD_B1_07||LPUART3_RX||UART BT HCI|
The MIMXRT1050 SoC is configured to use the 24 MHz external oscillator on the board with the on-chip PLL to generate a 600 MHz core clock.
The MIMXRT1050 SoC has eight UARTs.
LPUART1 is configured for the console,
LPUART3 for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
Programming and Debugging¶
The MIMXRT1050-EVK includes the NXP OpenSDA serial and debug adapter built into the board to provide debugging, flash programming, and serial communication over USB.
To use the Segger J-Link tools with OpenSDA, follow the instructions in the
Segger J-Link page using the Segger J-Link OpenSDA V2.1 Firmware.
The Segger J-Link tools are the default for this board, therefore it is not
necessary to set
OPENSDA_FW=jlink explicitly when you invoke
The pyOCD tools do not yet support this SoC.
The Segger J-Link firmware does not support command line flashing, therefore
flash build system target is not supported.
This example uses the Hello World sample with the Segger J-Link tools. Run the following to build your Zephyr application, invoke the J-Link GDB server, attach a GDB client, and program your Zephyr application to flash. It will leave you at a GDB prompt.
# On Linux/macOS cd $ZEPHYR_BASE/samples/hello_world mkdir build && cd build # On Windows cd %ZEPHYR_BASE%\samples\hello_world mkdir build & cd build # Use cmake to configure a Ninja-based build system: cmake -GNinja -DBOARD=mimxrt1050_evk .. # Now run ninja on the generated build system: ninja debug
The original MIMXRT1050-EVK (rev A0) board was updated with a newer MIMXRT1050-EVKB (rev A1) board, with these major hardware differences:
- SoC changed from MIMXRT1052DVL6**A** to MIMXRT1052DVL6**B** - Hardware bug fixes for: power, interfaces, and memory - Arduino headers included
For more details, please see the following NXP i.MXRT1050 A0 to A1 Migration Guide.
Current Zephyr build supports the new MIMXRT1050-EVKB