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riscv,sifive-e51

Vendor: RISC-V Foundation

Description

SiFive E51 Standard Core CPU

Properties

Properties not inherited from the base binding file.

Name

Type

Details

hardware-exec-breakpoint-count

int

Number of hardware break points

mmu-type

string

Memory Management Unit (MMU)

Legal values: 'riscv,sv32', 'riscv,sv39', 'riscv,sv48', 'riscv,none'

riscv,isa

string

RISC-V instruction set architecture

This property is required.

Legal values: 'rv32imac', 'rv32imafc', 'rv32imafcb', 'rv64imac', 'rv64imafdc'

clock-frequency

int

Clock frequency in Hz

cpu-power-states

phandles

List of power management states supported by this cpu

i-cache-line-size

int

i-cache line size

d-cache-line-size

int

d-cache line size