irq.h

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/*
 * Copyright (c) 2013-2014 Wind River Systems, Inc.
 * Copyright (c) 2019 Nordic Semiconductor ASA.
 * Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_
 
#include <zephyr/sw_isr_table.h>
#include <stdbool.h>
#if !defined(_ASMLANGUAGE) && defined(CONFIG_CPU_CORTEX_M)
#include <zephyr/arch/arm/arm-m-switch.h>
#endif
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifdef _ASMLANGUAGE
#if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) || defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
#define arch_irq_enable                     z_soc_irq_enable
#define arch_irq_disable                    z_soc_irq_disable
#define arch_irq_is_enabled                 z_soc_irq_is_enabled
#else
#define arch_irq_enable                     arm_irq_enable
#define arch_irq_disable                    arm_irq_disable
#define arch_irq_is_enabled                 arm_irq_is_enabled
#endif
#ifndef CONFIG_USE_SWITCH
GTEXT(z_arm_int_exit);
#endif
GTEXT(arch_irq_enable)
GTEXT(arch_irq_disable)
GTEXT(arch_irq_is_enabled)
#if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
GTEXT(z_soc_irq_get_active)
GTEXT(z_soc_irq_eoi)
#endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
#else
 
#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
extern void arm_irq_enable(unsigned int irq);
extern void arm_irq_disable(unsigned int irq);
extern int arm_irq_is_enabled(unsigned int irq);
extern void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags);
#if !defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
#define arch_irq_enable(irq)                     arm_irq_enable(irq)
#define arch_irq_disable(irq)                    arm_irq_disable(irq)
#define arch_irq_is_enabled(irq)                 arm_irq_is_enabled(irq)
#define z_arm_irq_priority_set(irq, prio, flags) arm_irq_priority_set(irq, prio, flags)
#endif
#endif
 
#if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) || defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
/*
 * When a custom interrupt controller or multi-level interrupts is specified,
 * map the architecture interrupt control functions to the SoC layer interrupt
 * control functions.
 */
 
void z_soc_irq_init(void);
void z_soc_irq_enable(unsigned int irq);
void z_soc_irq_disable(unsigned int irq);
int z_soc_irq_is_enabled(unsigned int irq);
 
void z_soc_irq_priority_set(
        unsigned int irq, unsigned int prio, unsigned int flags);
 
unsigned int z_soc_irq_get_active(void);
void z_soc_irq_eoi(unsigned int irq);
 
#define arch_irq_enable(irq)            z_soc_irq_enable(irq)
#define arch_irq_disable(irq)           z_soc_irq_disable(irq)
#define arch_irq_is_enabled(irq)        z_soc_irq_is_enabled(irq)
 
#define z_arm_irq_priority_set(irq, prio, flags)        \
        z_soc_irq_priority_set(irq, prio, flags)
 
#endif
 
#if defined(CONFIG_CPU_CORTEX_M) && defined(CONFIG_USE_SWITCH)
static inline void z_arm_int_exit(void)
{
        arm_m_exc_tail();
}
#else
extern void z_arm_int_exit(void);
#endif
 
extern void z_arm_interrupt_init(void);
 
/* Flags for use with IRQ_CONNECT() */
#define IRQ_ZERO_LATENCY        BIT(0)
 
#ifdef CONFIG_CPU_CORTEX_M
 
#if defined(CONFIG_ZERO_LATENCY_LEVELS)
#define ZERO_LATENCY_LEVELS CONFIG_ZERO_LATENCY_LEVELS
#else
#define ZERO_LATENCY_LEVELS 1
#endif
 
#define _CHECK_PRIO(priority_p, flags_p) \
        BUILD_ASSERT(((flags_p & IRQ_ZERO_LATENCY) && \
                      ((ZERO_LATENCY_LEVELS == 1) || \
                       (priority_p < ZERO_LATENCY_LEVELS))) || \
                     (priority_p <= IRQ_PRIO_LOWEST), \
                     "Invalid interrupt priority. Values must not exceed IRQ_PRIO_LOWEST");
#else
#define _CHECK_PRIO(priority_p, flags_p)
#endif
 
/* All arguments must be computable by the compiler at build time.
 *
 * Z_ISR_DECLARE will populate the .intList section with the interrupt's
 * parameters, which will then be used by gen_irq_tables.py to create
 * the vector table and the software ISR table. This is all done at
 * build-time.
 *
 * We additionally set the priority in the interrupt controller at
 * runtime.
 */
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
{ \
        BUILD_ASSERT(!(flags_p & IRQ_ZERO_LATENCY), \
                        "ZLI interrupts must be registered using IRQ_DIRECT_CONNECT()"); \
        _CHECK_PRIO(priority_p, flags_p) \
        Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
        z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
}
 
#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
{ \
        BUILD_ASSERT(IS_ENABLED(CONFIG_ZERO_LATENCY_IRQS) || !(flags_p & IRQ_ZERO_LATENCY), \
                        "ZLI interrupt registered but feature is disabled"); \
        _CHECK_PRIO(priority_p, flags_p) \
        Z_ISR_DECLARE_DIRECT(irq_p, ISR_FLAG_DIRECT, isr_p); \
        z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
}
 
#ifdef CONFIG_PM
extern void _arch_isr_direct_pm(void);
#define ARCH_ISR_DIRECT_PM() _arch_isr_direct_pm()
#else
#define ARCH_ISR_DIRECT_PM() do { } while (false)
#endif
 
#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
 
#ifdef CONFIG_TRACING_ISR
extern void sys_trace_isr_enter(void);
extern void sys_trace_isr_exit(void);
#endif
 
static inline void arch_isr_direct_header(void)
{
#ifdef CONFIG_TRACING_ISR
        sys_trace_isr_enter();
#endif
}
 
static inline void arch_isr_direct_footer(int maybe_swap)
{
#ifdef CONFIG_TRACING_ISR
        sys_trace_isr_exit();
#endif
        if (maybe_swap != 0) {
                z_arm_int_exit();
        }
}
 
#define ARCH_ISR_DIAG_OFF \
        TOOLCHAIN_DISABLE_CLANG_WARNING(TOOLCHAIN_WARNING_EXTRA) \
        TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES) \
        TOOLCHAIN_DISABLE_IAR_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES)
#define ARCH_ISR_DIAG_ON \
        TOOLCHAIN_ENABLE_CLANG_WARNING(TOOLCHAIN_WARNING_EXTRA) \
        TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES) \
        TOOLCHAIN_ENABLE_IAR_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES)
 
#define ARCH_ISR_DIRECT_DECLARE(name) \
        static inline int name##_body(void); \
        ARCH_ISR_DIAG_OFF \
        __attribute__ ((interrupt ("IRQ"))) void name(void) \
        { \
                int check_reschedule; \
                ISR_DIRECT_HEADER(); \
                check_reschedule = name##_body(); \
                ISR_DIRECT_FOOTER(check_reschedule); \
        } \
        ARCH_ISR_DIAG_ON \
        static inline int name##_body(void)
 
#if defined(CONFIG_DYNAMIC_DIRECT_INTERRUPTS)
 
extern void z_arm_irq_direct_dynamic_dispatch_reschedule(void);
extern void z_arm_irq_direct_dynamic_dispatch_no_reschedule(void);

#define ARM_IRQ_DIRECT_DYNAMIC_CONNECT(irq_p, priority_p, flags_p, resch) \
        IRQ_DIRECT_CONNECT(irq_p, priority_p, \
                _CONCAT(z_arm_irq_direct_dynamic_dispatch_, resch), flags_p)
 
#endif /* CONFIG_DYNAMIC_DIRECT_INTERRUPTS */
 
#if defined(CONFIG_ARM_SECURE_FIRMWARE)
/* Architecture-specific definition for the target security
 * state of an NVIC IRQ line.
 */
typedef enum {
        IRQ_TARGET_STATE_SECURE = 0,
        IRQ_TARGET_STATE_NON_SECURE
} irq_target_state_t;
 
#endif /* CONFIG_ARM_SECURE_FIRMWARE */
 
#endif /* _ASMLANGUAGE */
 
#ifdef __cplusplus
}
#endif
 
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_ */