Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
cpu.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
7
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
8
#define ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
9
10
#include <
zephyr/sys/util_macro.h
>
11
#include <
stdbool.h
>
12
13
#define DAIFSET_FIQ_BIT BIT(0)
14
#define DAIFSET_IRQ_BIT BIT(1)
15
#define DAIFSET_ABT_BIT BIT(2)
16
#define DAIFSET_DBG_BIT BIT(3)
17
18
#define DAIFCLR_FIQ_BIT BIT(0)
19
#define DAIFCLR_IRQ_BIT BIT(1)
20
#define DAIFCLR_ABT_BIT BIT(2)
21
#define DAIFCLR_DBG_BIT BIT(3)
22
23
#define DAIF_FIQ_BIT BIT(6)
24
#define DAIF_IRQ_BIT BIT(7)
25
#define DAIF_ABT_BIT BIT(8)
26
#define DAIF_DBG_BIT BIT(9)
27
28
#define SPSR_DAIF_SHIFT (6)
29
#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
30
31
#define SPSR_MODE_EL0T (0x0)
32
#define SPSR_MODE_EL1T (0x4)
33
#define SPSR_MODE_EL1H (0x5)
34
#define SPSR_MODE_EL2T (0x8)
35
#define SPSR_MODE_EL2H (0x9)
36
#define SPSR_MODE_MASK (0xf)
37
38
39
#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
40
BIT(22) | BIT(18) | BIT(16) | \
41
BIT(11) | BIT(5) | BIT(4))
42
43
#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
44
BIT(22) | BIT(18) | BIT(16) | \
45
BIT(11) | BIT(5) | BIT(4))
46
47
#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
48
BIT(22) | BIT(20) | BIT(11))
49
50
#define SCTLR_M_BIT BIT(0)
51
#define SCTLR_A_BIT BIT(1)
52
#define SCTLR_C_BIT BIT(2)
53
#define SCTLR_SA_BIT BIT(3)
54
#define SCTLR_I_BIT BIT(12)
55
#define SCTLR_BR_BIT BIT(17)
56
57
#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
58
59
#define SCR_NS_BIT BIT(0)
60
#define SCR_IRQ_BIT BIT(1)
61
#define SCR_FIQ_BIT BIT(2)
62
#define SCR_EA_BIT BIT(3)
63
#define SCR_SMD_BIT BIT(7)
64
#define SCR_HCE_BIT BIT(8)
65
#define SCR_RW_BIT BIT(10)
66
#define SCR_ST_BIT BIT(11)
67
#define SCR_EEL2_BIT BIT(18)
68
69
#define SCR_RES1 (BIT(4) | BIT(5))
70
71
/* MPIDR */
72
#define MPIDR_AFFLVL_MASK (0xffULL)
73
74
#define MPIDR_AFF0_SHIFT (0)
75
#define MPIDR_AFF1_SHIFT (8)
76
#define MPIDR_AFF2_SHIFT (16)
77
#define MPIDR_AFF3_SHIFT (32)
78
79
#define MPIDR_AFF_MASK (GENMASK(23, 0) | GENMASK(39, 32))
80
81
#define MPIDR_AFFLVL(mpidr, aff_level) \
82
(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
83
84
#define GET_MPIDR() read_sysreg(mpidr_el1)
85
#define MPIDR_TO_CORE(mpidr) (mpidr & MPIDR_AFF_MASK)
86
87
#define MODE_EL_SHIFT (0x2)
88
#define MODE_EL_MASK (0x3)
89
90
#define MODE_EL3 (0x3)
91
#define MODE_EL2 (0x2)
92
#define MODE_EL1 (0x1)
93
#define MODE_EL0 (0x0)
94
95
#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
96
97
#define ESR_EC_SHIFT (26)
98
#define ESR_EC_MASK BIT_MASK(6)
99
#define ESR_ISS_SHIFT (0)
100
#define ESR_ISS_MASK BIT_MASK(25)
101
#define ESR_IL_SHIFT (25)
102
#define ESR_IL_MASK BIT_MASK(1)
103
104
#define GET_ESR_EC(esr) (((esr) >> ESR_EC_SHIFT) & ESR_EC_MASK)
105
#define GET_ESR_IL(esr) (((esr) >> ESR_IL_SHIFT) & ESR_IL_MASK)
106
#define GET_ESR_ISS(esr) (((esr) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)
107
108
#define CNTV_CTL_ENABLE_BIT BIT(0)
109
#define CNTV_CTL_IMASK_BIT BIT(1)
110
111
#define ID_AA64PFR0_EL0_SHIFT (0)
112
#define ID_AA64PFR0_EL1_SHIFT (4)
113
#define ID_AA64PFR0_EL2_SHIFT (8)
114
#define ID_AA64PFR0_EL3_SHIFT (12)
115
#define ID_AA64PFR0_ELX_MASK (0xf)
116
#define ID_AA64PFR0_SEL2_SHIFT (36)
117
#define ID_AA64PFR0_SEL2_MASK (0xf)
118
119
/*
120
* TODO: ACTLR is of class implementation defined. All core implementations
121
* in armv8a have the same implementation so far w.r.t few controls.
122
* When there will be differences we have to create core specific headers.
123
*/
124
#define ACTLR_EL3_CPUACTLR_BIT BIT(0)
125
#define ACTLR_EL3_CPUECTLR_BIT BIT(1)
126
#define ACTLR_EL3_L2CTLR_BIT BIT(4)
127
#define ACTLR_EL3_L2ECTLR_BIT BIT(5)
128
#define ACTLR_EL3_L2ACTLR_BIT BIT(6)
129
130
#define CPTR_EZ_BIT BIT(8)
131
#define CPTR_TFP_BIT BIT(10)
132
#define CPTR_TTA_BIT BIT(20)
133
#define CPTR_TCPAC_BIT BIT(31)
134
135
#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
136
137
#define HCR_FMO_BIT BIT(3)
138
#define HCR_IMO_BIT BIT(4)
139
#define HCR_AMO_BIT BIT(5)
140
#define HCR_TGE_BIT BIT(27)
141
#define HCR_RW_BIT BIT(31)
142
143
/* System register interface to GICv3 */
144
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
145
#define ICC_SGI1R S3_0_C12_C11_5
146
#define ICC_SRE_EL1 S3_0_C12_C12_5
147
#define ICC_SRE_EL2 S3_4_C12_C9_5
148
#define ICC_SRE_EL3 S3_6_C12_C12_5
149
#define ICC_CTLR_EL1 S3_0_C12_C12_4
150
#define ICC_CTLR_EL3 S3_6_C12_C12_4
151
#define ICC_PMR_EL1 S3_0_C4_C6_0
152
#define ICC_RPR_EL1 S3_0_C12_C11_3
153
#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
154
#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
155
#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
156
#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
157
#define ICC_IAR0_EL1 S3_0_C12_C8_0
158
#define ICC_IAR1_EL1 S3_0_C12_C12_0
159
#define ICC_EOIR0_EL1 S3_0_C12_C8_1
160
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
161
#define ICC_SGI0R_EL1 S3_0_C12_C11_7
162
163
/* register constants */
164
#define ICC_SRE_ELx_SRE_BIT BIT(0)
165
#define ICC_SRE_ELx_DFB_BIT BIT(1)
166
#define ICC_SRE_ELx_DIB_BIT BIT(2)
167
#define ICC_SRE_EL3_EN_BIT BIT(3)
168
169
/* ICC SGI macros */
170
#define SGIR_TGT_MASK (0xffff)
171
#define SGIR_AFF1_SHIFT (16)
172
#define SGIR_AFF2_SHIFT (32)
173
#define SGIR_AFF3_SHIFT (48)
174
#define SGIR_AFF_MASK (0xff)
175
#define SGIR_INTID_SHIFT (24)
176
#define SGIR_INTID_MASK (0xf)
177
#define SGIR_IRM_SHIFT (40)
178
#define SGIR_IRM_MASK (0x1)
179
#define SGIR_IRM_TO_AFF (0)
180
181
#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
182
((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
183
(((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
184
(((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
185
(((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
186
(((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
187
((_tgt) & SGIR_TGT_MASK))
188
189
/* Implementation defined register definitions */
190
#if defined(CONFIG_CPU_CORTEX_A72)
191
192
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
193
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT (0)
194
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT (5)
195
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT (6)
196
#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT (9)
197
198
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES (2)
199
#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK (0x7)
200
#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE (1)
201
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES (1)
202
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES (2)
203
#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK (0x7)
204
#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE (1)
205
206
#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
207
#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT BIT(6)
208
209
#endif
/* CONFIG_CPU_CORTEX_A72 */
210
211
#define L1_CACHE_SHIFT (6)
212
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
213
#define ARM64_CPU_INIT_SIZE L1_CACHE_BYTES
214
215
#endif
/* ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_ */
stdbool.h
util_macro.h
Macro utilities.
zephyr
arch
arm64
cpu.h
Generated on Fri Nov 8 2024 15:02:20 for Zephyr API Documentation by
1.12.0