Zephyr API Documentation 4.0.0-rc2
A Scalable Open Source RTOS
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cpu.h
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1/*
2 * Copyright (c) 2018 Lexmark International, Inc.
3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
9#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
10
11#if defined(CONFIG_ARM_MPU)
13#endif
14
15/*
16 * SCTLR register bit assignments
17 */
18#define SCTLR_MPU_ENABLE (1 << 0)
19
20#define MODE_USR 0x10
21#define MODE_FIQ 0x11
22#define MODE_IRQ 0x12
23#define MODE_SVC 0x13
24#define MODE_ABT 0x17
25#define MODE_HYP 0x1a
26#define MODE_UND 0x1b
27#define MODE_SYS 0x1f
28#define MODE_MASK 0x1f
29
30#define E_BIT (1 << 9)
31#define A_BIT (1 << 8)
32#define I_BIT (1 << 7)
33#define F_BIT (1 << 6)
34#define T_BIT (1 << 5)
35
36#define HIVECS (1 << 13)
37
38#define CPACR_NA (0U)
39#define CPACR_FA (3U)
40
41#define CPACR_CP10(r) (r << 20)
42#define CPACR_CP11(r) (r << 22)
43
44#define FPEXC_EN (1 << 30)
45
46#define DFSR_DOMAIN_SHIFT (4)
47#define DFSR_DOMAIN_MASK (0xf)
48#define DFSR_FAULT_4_MASK (1 << 10)
49#define DFSR_WRITE_MASK (1 << 11)
50#define DFSR_AXI_SLAVE_MASK (1 << 12)
51
52/* Armv8-R AArch32 architecture profile */
53#define VBAR_MASK (0xFFFFFFE0U)
54#define SCTLR_M_BIT BIT(0)
55#define SCTLR_A_BIT BIT(1)
56#define SCTLR_C_BIT BIT(2)
57#define SCTLR_I_BIT BIT(12)
58
59/* Hyp System Control Register */
60#define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \
61 BIT(22) | BIT(18) | BIT(16) | \
62 BIT(11) | BIT(4) | BIT(3))
63
64/* Hyp Auxiliary Control Register */
65#define HACTLR_CPUACTLR BIT(0)
66#define HACTLR_CDBGDCI BIT(1)
67#define HACTLR_FLASHIFREGIONR BIT(7)
68#define HACTLR_PERIPHPREGIONR BIT(8)
69#define HACTLR_QOSR_BIT BIT(9)
70#define HACTLR_BUSTIMEOUTR_BIT BIT(10)
71#define HACTLR_INTMONR_BIT BIT(12)
72#define HACTLR_ERR_BIT BIT(13)
73
74#define HACTLR_INIT (HACTLR_ERR_BIT | HACTLR_INTMONR_BIT | \
75 HACTLR_BUSTIMEOUTR_BIT | HACTLR_QOSR_BIT | \
76 HACTLR_PERIPHPREGIONR | HACTLR_FLASHIFREGIONR | \
77 HACTLR_CDBGDCI | HACTLR_CPUACTLR)
78/* ARMv8 Timer */
79#define CNTV_CTL_ENABLE_BIT BIT(0)
80#define CNTV_CTL_IMASK_BIT BIT(1)
81
82/* Interrupt Controller System Register Enable Register */
83#define ICC_SRE_ELx_SRE_BIT BIT(0)
84#define ICC_SRE_ELx_DFB_BIT BIT(1)
85#define ICC_SRE_ELx_DIB_BIT BIT(2)
86#define ICC_SRE_EL3_EN_BIT BIT(3)
87
88/* MPIDR mask to extract Aff0, Aff1, and Aff2 */
89#define MPIDR_AFFLVL_MASK (0xffffff)
90
91#define MPIDR_AFF0_SHIFT (0)
92#define MPIDR_AFF1_SHIFT (8)
93#define MPIDR_AFF2_SHIFT (16)
94
95#define MPIDR_AFFLVL(mpidr, aff_level) \
96 (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
97
98#define GET_MPIDR() read_sysreg(mpidr)
99#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
100
101/* ICC SGI macros */
102#define SGIR_TGT_MASK (0xffff)
103#define SGIR_AFF1_SHIFT (16)
104#define SGIR_AFF2_SHIFT (32)
105#define SGIR_AFF3_SHIFT (48)
106#define SGIR_AFF_MASK (0xff)
107#define SGIR_INTID_SHIFT (24)
108#define SGIR_INTID_MASK (0xf)
109#define SGIR_IRM_SHIFT (40)
110#define SGIR_IRM_MASK (0x1)
111#define SGIR_IRM_TO_AFF (0)
112
113#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
114 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
115 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
116 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
117 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
118 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
119 ((_tgt) & SGIR_TGT_MASK))
120
121#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_ */