Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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cpu.h
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/*
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* Copyright (c) 2018 Lexmark International, Inc.
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* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_
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#if defined(CONFIG_ARM_MPU)
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#include <
zephyr/arch/arm/cortex_a_r/mpu.h
>
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#endif
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/*
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* SCTLR register bit assignments
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*/
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#define SCTLR_MPU_ENABLE (1 << 0)
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#define MODE_USR 0x10
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#define MODE_FIQ 0x11
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#define MODE_IRQ 0x12
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#define MODE_SVC 0x13
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#define MODE_ABT 0x17
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#define MODE_HYP 0x1a
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#define MODE_UND 0x1b
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#define MODE_SYS 0x1f
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#define MODE_MASK 0x1f
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#define E_BIT (1 << 9)
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#define A_BIT (1 << 8)
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#define I_BIT (1 << 7)
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#define F_BIT (1 << 6)
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#define T_BIT (1 << 5)
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#define HIVECS (1 << 13)
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#define CPACR_NA (0U)
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#define CPACR_FA (3U)
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#define CPACR_CP10(r) (r << 20)
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#define CPACR_CP11(r) (r << 22)
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#define FPEXC_EN (1 << 30)
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#define DFSR_DOMAIN_SHIFT (4)
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#define DFSR_DOMAIN_MASK (0xf)
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#define DFSR_FAULT_4_MASK (1 << 10)
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#define DFSR_WRITE_MASK (1 << 11)
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#define DFSR_AXI_SLAVE_MASK (1 << 12)
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/* Armv8-R AArch32 architecture profile */
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#define VBAR_MASK (0xFFFFFFE0U)
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#define SCTLR_M_BIT BIT(0)
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#define SCTLR_A_BIT BIT(1)
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#define SCTLR_C_BIT BIT(2)
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#define SCTLR_I_BIT BIT(12)
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/* Hyp System Control Register */
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#define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(4) | BIT(3))
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/* Hyp Auxiliary Control Register */
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#define HACTLR_CPUACTLR BIT(0)
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#define HACTLR_CDBGDCI BIT(1)
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#define HACTLR_FLASHIFREGIONR BIT(7)
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#define HACTLR_PERIPHPREGIONR BIT(8)
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#define HACTLR_QOSR_BIT BIT(9)
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#define HACTLR_BUSTIMEOUTR_BIT BIT(10)
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#define HACTLR_INTMONR_BIT BIT(12)
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#define HACTLR_ERR_BIT BIT(13)
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#define HACTLR_INIT (HACTLR_ERR_BIT | HACTLR_INTMONR_BIT | \
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HACTLR_BUSTIMEOUTR_BIT | HACTLR_QOSR_BIT | \
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HACTLR_PERIPHPREGIONR | HACTLR_FLASHIFREGIONR | \
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HACTLR_CDBGDCI | HACTLR_CPUACTLR)
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/* ARMv8 Timer */
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#define CNTV_CTL_ENABLE_BIT BIT(0)
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#define CNTV_CTL_IMASK_BIT BIT(1)
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/* Interrupt Controller System Register Enable Register */
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#define ICC_SRE_ELx_SRE_BIT BIT(0)
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#define ICC_SRE_ELx_DFB_BIT BIT(1)
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#define ICC_SRE_ELx_DIB_BIT BIT(2)
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#define ICC_SRE_EL3_EN_BIT BIT(3)
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/* MPIDR mask to extract Aff0, Aff1, and Aff2 */
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#define MPIDR_AFFLVL_MASK (0xffffff)
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#define MPIDR_AFF0_SHIFT (0)
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#define MPIDR_AFF1_SHIFT (8)
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#define MPIDR_AFF2_SHIFT (16)
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#define MPIDR_AFFLVL(mpidr, aff_level) \
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(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
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#define GET_MPIDR() read_sysreg(mpidr)
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#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
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/* ICC SGI macros */
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#define SGIR_TGT_MASK (0xffff)
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#define SGIR_AFF1_SHIFT (16)
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#define SGIR_AFF2_SHIFT (32)
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#define SGIR_AFF3_SHIFT (48)
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#define SGIR_AFF_MASK (0xff)
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#define SGIR_INTID_SHIFT (24)
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#define SGIR_INTID_MASK (0xf)
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#define SGIR_IRM_SHIFT (40)
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#define SGIR_IRM_MASK (0x1)
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#define SGIR_IRM_TO_AFF (0)
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#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
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((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
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(((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
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(((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
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(((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
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(((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
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((_tgt) & SGIR_TGT_MASK))
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#endif
/* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_CPU_H_ */
mpu.h
zephyr
arch
arm
cortex_a_r
cpu.h
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