Zephyr API Documentation
4.0.0-rc2
A Scalable Open Source RTOS
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cpu.h
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CORTEX_M_CPU_H
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#define _CORTEX_M_CPU_H
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#ifdef _ASMLANGUAGE
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#define _SCS_BASE_ADDR _PPB_INT_SCS
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/* ICSR defines */
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#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
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#define _SCS_ICSR_PENDSV (1 << 28)
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#define _SCS_ICSR_UNPENDSV (1 << 27)
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#define _SCS_ICSR_RETTOBASE (1 << 11)
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#define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94)
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/* CONTROL defines */
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#define _CONTROL_FPCA_Msk (1 << 2)
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/* EXC_RETURN defines */
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#define _EXC_RETURN_SPSEL_Msk (1 << 2)
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#define _EXC_RETURN_FTYPE_Msk (1 << 4)
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#else
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#include <
stdint.h
>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* CP10 Access Bits */
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#define CPACR_CP10_Pos 20U
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#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos)
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#define CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos)
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#define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
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#define CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos)
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#define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
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/* CP11 Access Bits */
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#define CPACR_CP11_Pos 22U
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#define CPACR_CP11_Msk (3UL << CPACR_CP11_Pos)
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#define CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos)
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#define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
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#define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos)
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#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
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#ifdef CONFIG_PM_S2RAM
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struct
__cpu_context {
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/* GPRs are saved onto the stack */
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uint32_t
msp;
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uint32_t
msplim;
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uint32_t
psp;
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uint32_t
psplim;
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uint32_t
apsr;
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uint32_t
ipsr;
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uint32_t
epsr;
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uint32_t
primask;
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uint32_t
faultmask;
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uint32_t
basepri;
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uint32_t
control;
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};
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typedef
struct
__cpu_context _cpu_context_t;
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#endif
/* CONFIG_PM_S2RAM */
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _ASMLANGUAGE */
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#endif
/* _CORTEX_M_CPU_H */
stdint.h
uint32_t
__UINT32_TYPE__ uint32_t
Definition
stdint.h:90
zephyr
arch
arm
cortex_m
cpu.h
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