Zephyr API Documentation 4.3.99
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arm_mpu_v8.h
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1/*
2 * Copyright (c) 2018 Linaro Limited.
3 * Copyright (c) 2018 Nordic Semiconductor ASA.
4 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#ifndef _ASMLANGUAGE
10
11/* Convenience macros to represent the ARMv8-M-specific
12 * configuration for memory access permission and
13 * cache-ability attribution.
14 */
15#if defined(CONFIG_AARCH32_ARMV8_R)
16#define MPU_IR_REGION_Msk (0xFFU)
17#define MPU_IR_REGION_Pos 8U
18/* MPU RBAR Register attribute msk Definitions */
19#define MPU_RBAR_BASE_Pos 6U
20#define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
21#define MPU_RBAR_SH_Pos 3U
22#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
23#define MPU_RBAR_AP_Pos 1U
24#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
25/* RBAR XN */
26#define MPU_RBAR_XN_Pos 0U
27#define MPU_RBAR_XN_Msk (0x1UL << MPU_RBAR_XN_Pos)
28
29/* MPU PLBAR Register Definitions */
30#define MPU_RLAR_LIMIT_Pos 6U
31#define MPU_RLAR_LIMIT_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
32#define MPU_RLAR_AttrIndx_Pos 1U
33#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
34#define MPU_RLAR_EN_Msk (0x1UL)
35#else
36#include <cmsis_core.h>
37#endif
38
39/* Privileged No Access, Unprivileged No Access */
40/*#define NO_ACCESS 0x0 */
41/*#define NO_ACCESS_Msk ((NO_ACCESS << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
42/* Privileged No Access, Unprivileged No Access */
43/*#define P_NA_U_NA 0x0 */
44/*#define P_NA_U_NA_Msk ((P_NA_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) */
45/* Privileged Read Write, Unprivileged No Access */
46#define P_RW_U_NA 0x0
47#define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
48/* Privileged Read Write, Unprivileged Read Only */
49/*#define P_RW_U_RO 0x2 */
50/*#define P_RW_U_RO_Msk ((P_RW_U_RO << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)*/
51/* Privileged Read Write, Unprivileged Read Write */
52#define P_RW_U_RW 0x1
53#define P_RW_U_RW_Msk ((P_RW_U_RW << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
54/* Privileged Read Write, Unprivileged Read Write */
55#define FULL_ACCESS 0x1
56#define FULL_ACCESS_Msk ((FULL_ACCESS << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
57/* Privileged Read Only, Unprivileged No Access */
58#define P_RO_U_NA 0x2
59#define P_RO_U_NA_Msk ((P_RO_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
60/* Privileged Read Only, Unprivileged Read Only */
61#define P_RO_U_RO 0x3
62#define P_RO_U_RO_Msk ((P_RO_U_RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
63/* Privileged Read Only, Unprivileged Read Only */
64#define RO 0x3
65#define RO_Msk ((RO << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk)
66
67/* Attribute flag for not-allowing execution (eXecute Never) */
68#define NOT_EXEC MPU_RBAR_XN_Msk
69
70/* To prevent execution of MPU region in privileged mode */
71#define PRIV_EXEC_NEVER (1)
72
73/* Attribute flags for share-ability */
74#define NON_SHAREABLE 0x0
75#define NON_SHAREABLE_Msk ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
76#define OUTER_SHAREABLE 0x2
77#define OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
78#define INNER_SHAREABLE 0x3
79#define INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
80
81/* Helper define to calculate the region limit address. */
82#define REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
83
84/* Attribute flags for cache-ability */
85
86/* Memory Attributes for Device Memory
87 * 1.Gathering (G/nG)
88 * Determines whether multiple accesses can be merged into a single
89 * bus transaction.
90 * nG: Number/size of accesses on the bus = number/size of accesses
91 * in code.
92 *
93 * 2.Reordering (R/nR)
94 * Determines whether accesses to the same device can be reordered.
95 * nR: Accesses to the same IMPLEMENTATION DEFINED block size will
96 * appear on the bus in program order.
97 *
98 * 3 Early Write Acknowledgment (E/nE)
99 * Indicates to the memory system whether a buffer can send
100 * acknowledgements.
101 * nE: The response should come from the end slave, not buffering in
102 * the interconnect.
103 */
104#define DEVICE_nGnRnE 0x0U
105#define DEVICE_nGnRE 0x4U
106#define DEVICE_nGRE 0x8U
107#define DEVICE_GRE 0xCU
108
109/* Read/Write Allocation Configurations for Cacheable Memory */
110#define R_NON_W_NON 0x0 /* Do not allocate Read/Write */
111#define R_NON_W_ALLOC 0x1 /* Do not allocate Read, Allocate Write */
112#define R_ALLOC_W_NON 0x2 /* Allocate Read, Do not allocate Write */
113#define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */
114
115/* Memory Attributes for Normal Memory */
116#define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */
117#define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */
118#define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable */
119
120#define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */
121#define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */
122#define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable */
123
124#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \
125 ((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | (NORMAL_I_WT_NT | R_ALLOC_W_NON))
126
127#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \
128 ((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
129
130#define NORMAL_OUTER_INNER_NON_CACHEABLE \
131 ((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | (NORMAL_I_NON_C | R_NON_W_NON))
132
133/* Common cache-ability configuration for Flash, SRAM regions */
134#define MPU_CACHE_ATTRIBUTES_FLASH NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
135/* clang-format off */
136#define MPU_CACHE_ATTRIBUTES_SRAM \
137 NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
138/* clang-format on */
139#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE NORMAL_OUTER_INNER_NON_CACHEABLE
140
141/* Global MAIR configurations */
142#define MPU_MAIR_ATTR_FLASH MPU_CACHE_ATTRIBUTES_FLASH
143#define MPU_MAIR_INDEX_FLASH 0
144#define MPU_MAIR_ATTR_SRAM MPU_CACHE_ATTRIBUTES_SRAM
145#define MPU_MAIR_INDEX_SRAM 1
146#define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE
147#define MPU_MAIR_INDEX_SRAM_NOCACHE 2
148#define MPU_MAIR_ATTR_DEVICE DEVICE_nGnRnE
149#define MPU_MAIR_INDEX_DEVICE 3
150/* Flash region(s): Attribute-0
151 * SRAM region(s): Attribute-1
152 * SRAM no cache-able regions(s): Attribute-2
153 * DEVICE no cache-able regions(s): Attribute-3
154 */
155#define MPU_MAIR_ATTRS \
156 ((MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) | \
157 (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \
158 (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) | \
159 (MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)))
160
161/* Some helper defines for common regions.
162 *
163 * Note that the ARMv8-M/R MPU architecture requires that the
164 * enabled MPU regions are non-overlapping. Therefore, it is
165 * recommended to use these helper defines only for configuring
166 * fixed MPU regions at build-time (i.e. regions that are not
167 * expected to be re-programmed or re-adjusted at run-time so
168 * that they do not overlap with other MPU regions).
169 */
170#if defined(CONFIG_AARCH32_ARMV8_R)
171
172#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
173 { \
174 .name = p_name, \
175 .base = p_base, \
176 .attr = p_attr(p_base + p_size), \
177 }
178
179#define REGION_RAM_ATTR(limit) \
180 { \
181 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
182 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
183 .r_limit = limit - 1, /* Region Limit */ \
184 }
185
186#define REGION_RAM_TEXT_ATTR(limit) \
187 { \
188 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
189 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
190 .r_limit = limit - 1, /* Region Limit */ \
191 }
192
193#define REGION_RAM_RO_ATTR(limit) \
194 { \
195 .rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
196 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
197 .r_limit = limit - 1, /* Region Limit */ \
198 }
199#define REGION_RAM_NOCACHE_ATTR(limit) \
200 { \
201 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
202 .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
203 .r_limit = limit - 1, /* Region Limit */ \
204 }
205#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
206/* Note that the access permissions allow for un-privileged writes, contrary
207 * to ARMv7-M where un-privileged code has Read-Only permissions.
208 */
209#define REGION_FLASH_ATTR(limit) \
210 { \
211 .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
212 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
213 .r_limit = limit - 1, /* Region Limit */ \
214 }
215#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
216#define REGION_FLASH_ATTR(limit) \
217 { \
218 .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
219 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
220 .r_limit = limit - 1, /* Region Limit */ \
221 }
222#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
223
224#define REGION_DEVICE_ATTR(limit) \
225 { \
226 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
227 .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
228 .r_limit = limit - 1, /* Region Limit */ \
229 }
230#else
231
232#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr) \
233 { \
234 .name = p_name, \
235 .base = p_base, \
236 .attr = p_attr(p_base, p_size), \
237 }
238
239/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
240 * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
241 * the SRAM region XN bit clear or the application code will not be executable.
242 */
243/* clang-format off */
244#define REGION_RAM_ATTR(base, size) \
245 { \
246 .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk | \
247 NON_SHAREABLE_Msk, /* AP, XN, SH */ \
248 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
249 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
250 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
251 }
252
253#define REGION_RAM_WT_ATTR(base, size) \
254 { \
255 .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk | \
256 NON_SHAREABLE_Msk, /* AP, XN, SH */ \
257 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
258 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
259 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
260 }
261
262#if defined(CONFIG_ARM_MPU_PXN)
263/* Use this attr to define an MPU region in RAM that has code intended to be executed in
264 * un-privileged mode but not in privileged mode.
265 */
266#define REGION_RAM_ATTR_PXN(base, size) \
267 { \
268 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */ \
269 .mair_idx = MPU_MAIR_INDEX_SRAM, /* Cache-ability */ \
270 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
271 .pxn = PRIV_EXEC_NEVER, \
272 }
273
274#define REGION_RAM_WT_ATTR_PXN(base, size) \
275 { \
276 .rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */ \
277 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
278 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
279 .pxn = PRIV_EXEC_NEVER, \
280 }
281#endif
282
283#define REGION_RAM_NOCACHE_ATTR(base, size) \
284 { \
285 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
286 .mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, /* Cache-ability */ \
287 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
288 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
289 }
290
291#if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
292/* Note that the access permissions allow for un-privileged writes, contrary
293 * to ARMv7-M where un-privileged code has Read-Only permissions.
294 */
295#define REGION_FLASH_ATTR(base, size) \
296 { \
297 .rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
298 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
299 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
300 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
301 }
302
303#else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
304#define REGION_FLASH_ATTR(base, size) \
305 { \
306 .rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
307 .mair_idx = MPU_MAIR_INDEX_FLASH, /* Cache-ability */ \
308 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
309 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,)) \
310 }
311
312#endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
313
314#define REGION_DEVICE_ATTR(base, size) \
315 { \
316 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
317 .mair_idx = MPU_MAIR_INDEX_DEVICE, /* Cache-ability */ \
318 .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \
319 IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,)) \
320 }
321
322/* clang-format on */
323#endif
324
325struct arm_mpu_region_attr {
326 /* Attributes belonging to RBAR */
327 uint8_t rbar: 5;
328 /* MAIR index for attribute indirection */
329 uint8_t mair_idx: 3;
330 /* Region Limit Address value to be written to the RLAR register. */
331 uint32_t r_limit;
332#ifdef CONFIG_ARM_MPU_PXN
333 /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
334 uint8_t pxn;
335#endif
336};
337
338typedef struct arm_mpu_region_attr arm_mpu_region_attr_t;
339
340/* Typedef for the k_mem_partition attribute */
341typedef struct {
342 uint16_t rbar;
343 uint16_t mair_idx;
344#ifdef CONFIG_ARM_MPU_PXN
345 /* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
346 uint8_t pxn;
347#endif
348} k_mem_partition_attr_t;
349
350/* Kernel macros for memory attribution
351 * (access permissions and cache-ability).
352 *
353 * The macros are to be stored in k_mem_partition_attr_t
354 * objects. The format of a k_mem_partition_attr_t object
355 * is as follows: field <rbar> contains a direct mapping
356 * of the <XN> and <AP> bit-fields of the RBAR register;
357 * field <mair_idx> contains a direct mapping of AttrIdx
358 * bit-field, stored in RLAR register.
359 */
360
361/* Read-Write access permission attributes */
362#define K_MEM_PARTITION_P_RW_U_RW \
363 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
364#define K_MEM_PARTITION_P_RW_U_NA \
365 ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
366#define K_MEM_PARTITION_P_RO_U_RO \
367 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
368#define K_MEM_PARTITION_P_RO_U_NA \
369 ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
370
371/* Execution-allowed attributes */
372#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t){(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
373#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
374
375#ifdef CONFIG_ARM_MPU_PXN
376#define K_MEM_PARTITION_P_R_U_RX \
377 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM, PRIV_EXEC_NEVER})
378#endif
379
380/*
381 * @brief Evaluate Write-ability
382 *
383 * Evaluate whether the access permissions include write-ability.
384 *
385 * @param attr The k_mem_partition_attr_t object holding the
386 * MPU attributes to be checked against write-ability.
387 */
388#define K_MEM_PARTITION_IS_WRITABLE(attr) \
389 ({ \
390 int __is_writable__; \
391 switch (attr.rbar & MPU_RBAR_AP_Msk) { \
392 case P_RW_U_RW_Msk: \
393 case P_RW_U_NA_Msk: \
394 __is_writable__ = 1; \
395 break; \
396 default: \
397 __is_writable__ = 0; \
398 } \
399 __is_writable__; \
400 })
401
402/*
403 * @brief Evaluate Execution allowance
404 *
405 * Evaluate whether the access permissions include execution.
406 *
407 * @param attr The k_mem_partition_attr_t object holding the
408 * MPU attributes to be checked against execution
409 * allowance.
410 */
411#define K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rbar) & (NOT_EXEC)))
412
413/* Attributes for no-cache enabling (share-ability is selected by default) */
414
415/* Read-Write access permission attributes */
416#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE \
417 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
418 MPU_MAIR_INDEX_SRAM_NOCACHE})
419#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE \
420 ((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
421 MPU_MAIR_INDEX_SRAM_NOCACHE})
422#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE \
423 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
424 MPU_MAIR_INDEX_SRAM_NOCACHE})
425#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE \
426 ((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
427 MPU_MAIR_INDEX_SRAM_NOCACHE})
428
429/* Execution-allowed attributes */
430#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE \
431 ((k_mem_partition_attr_t){(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), \
432 MPU_MAIR_INDEX_SRAM_NOCACHE})
433#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE \
434 ((k_mem_partition_attr_t){(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), \
435 MPU_MAIR_INDEX_SRAM_NOCACHE})
436
437#endif /* _ASMLANGUAGE */
438
439
440/* Some compilers do not handle casts on pointers in constant expressions */
441#if defined(__IAR_SYSTEMS_ICC__)
442#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
443 BUILD_ASSERT( \
444 (size > 0) && \
445 ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
446 "The start and size of the partition must align with the minimum MPU " \
447 "region size.")
448#else
449#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
450 BUILD_ASSERT((size > 0) && \
451 ((uint32_t)start % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
452 ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
453 "The start and size of the partition must align with the minimum MPU " \
454 "region size.")
455#endif /* defined(__IAR_SYSTEMS_ICC__) */
arm_mpu_region_attr_t
struct arm_mpu_region_attr arm_mpu_region_attr_t
Definition arm_mpu_v7m.h:142
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
uint16_t
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
arm_mpu_region_attr
Definition arm_mpu_v7m.h:137
arm_mpu_region_attr::rbar
uint8_t rbar
Definition arm_mpu_v8.h:327
arm_mpu_region_attr::r_limit
uint32_t r_limit
Definition arm_mpu_v8.h:331
arm_mpu_region_attr::mair_idx
uint8_t mair_idx
Definition arm_mpu_v8.h:329
k_mem_partition_attr_t
Definition arm_mpu_v7m.h:145
k_mem_partition_attr_t::rbar
uint16_t rbar
Definition arm_mpu_v8.h:342
k_mem_partition_attr_t::mair_idx
uint16_t mair_idx
Definition arm_mpu_v8.h:343