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4.0.0-rc2
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aux_regs.h
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
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#define ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_
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#include <
zephyr/sys/util_macro.h
>
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#define _ARC_V2_LP_START 0x002
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#define _ARC_V2_LP_END 0x003
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#define _ARC_V2_IDENTITY 0x004
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#define _ARC_V2_SEC_STAT 0x09
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#define _ARC_V2_STATUS32 0x00a
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#define _ARC_V2_STATUS32_P0 0x00b
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#define _ARC_V2_USER_SP 0x00d
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#define _ARC_V2_AUX_IRQ_CTRL 0x00e
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#define _ARC_V2_IC_IVIC 0x010
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#define _ARC_V2_IC_CTRL 0x011
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#define _ARC_V2_IC_LIL 0x013
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#define _ARC_V2_IC_IVIL 0x019
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#define _ARC_V2_IC_DATA 0x01d
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#define _ARC_V2_TMR0_COUNT 0x021
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#define _ARC_V2_TMR0_CONTROL 0x022
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#define _ARC_V2_TMR0_LIMIT 0x023
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#define _ARC_V2_IRQ_VECT_BASE 0x025
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#define _ARC_V2_IRQ_VECT_BASE_S 0x26
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#define _ARC_V2_KERNEL_SP 0x38
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#define _ARC_V2_SEC_U_SP 0x39
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#define _ARC_V2_SEC_K_SP 0x3a
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#define _ARC_V2_AUX_IRQ_ACT 0x043
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#define _ARC_V2_DC_IVDC 0x047
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#define _ARC_V2_DC_CTRL 0x048
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#define _ARC_V2_DC_LDL 0x049
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#define _ARC_V2_DC_IVDL 0x04a
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#define _ARC_V2_DC_FLSH 0x04b
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#define _ARC_V2_DC_FLDL 0x04c
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#define _ARC_V2_EA_BUILD 0x065
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#define _ARC_V2_VECBASE_AC_BUILD 0x068
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#define _ARC_V2_FP_BUILD 0x06b
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#define _ARC_V2_DPFP_BUILD 0x06c
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#define _ARC_V2_MPU_BUILD 0x06d
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#define _ARC_V2_RF_BUILD 0x06e
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#define _ARC_V2_MMU_BUILD 0x06f
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#define _ARC_V2_VECBASE_BUILD 0x071
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#define _ARC_V2_D_CACHE_BUILD 0x072
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#define _ARC_V2_DCCM_BUILD 0x074
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#define _ARC_V2_TIMER_BUILD 0x075
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#define _ARC_V2_AP_BUILD 0x076
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#define _ARC_V2_I_CACHE_BUILD 0x077
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#define _ARC_V2_ICCM_BUILD 0x078
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#define _ARC_V2_MULTIPLY_BUILD 0x07b
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#define _ARC_V2_SWAP_BUILD 0x07c
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#define _ARC_V2_NORM_BUILD 0x07d
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#define _ARC_V2_MINMAX_BUILD 0x07e
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#define _ARC_V2_BARREL_BUILD 0x07f
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#define _ARC_V2_ISA_CONFIG 0x0c1
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#define _ARC_V2_SEP_BUILD 0x0c7
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#define _ARC_V2_LPB_BUILD 0x0e9
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#define _ARC_V2_LPB_CTRL 0x488
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#define _ARC_V2_IRQ_BUILD 0x0f3
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#define _ARC_V2_PCT_BUILD 0x0f5
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#define _ARC_V2_CC_BUILD 0x0f6
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#define _ARC_V2_TMR1_COUNT 0x100
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#define _ARC_V2_TMR1_CONTROL 0x101
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#define _ARC_V2_TMR1_LIMIT 0x102
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#define _ARC_V2_S_TMR0_COUNT 0x106
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#define _ARC_V2_S_TMR0_CONTROL 0x107
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#define _ARC_V2_S_TMR0_LIMIT 0x108
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#define _ARC_V2_S_TMR1_COUNT 0x109
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#define _ARC_V2_S_TMR1_CONTROL 0x10a
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#define _ARC_V2_S_TMR1_LIMIT 0x10b
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#define _ARC_V2_IRQ_PRIO_PEND 0x200
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#define _ARC_V2_AUX_IRQ_HINT 0x201
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#define _ARC_V2_IRQ_PRIORITY 0x206
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#define _ARC_V2_USTACK_TOP 0x260
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#define _ARC_V2_USTACK_BASE 0x261
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#define _ARC_V2_S_USTACK_TOP 0x262
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#define _ARC_V2_S_USTACK_BASE 0x263
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#define _ARC_V2_KSTACK_TOP 0x264
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#define _ARC_V2_KSTACK_BASE 0x265
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#define _ARC_V2_S_KSTACK_TOP 0x266
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#define _ARC_V2_S_KSTACK_BASE 0x267
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#define _ARC_V2_NSC_TABLE_TOP 0x268
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#define _ARC_V2_NSC_TABLE_BASE 0x269
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#define _ARC_V2_JLI_BASE 0x290
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#define _ARC_V2_LDI_BASE 0x291
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#define _ARC_V2_EI_BASE 0x292
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#define _ARC_V2_ERET 0x400
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#define _ARC_V2_ERSTATUS 0x402
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#define _ARC_V2_ECR 0x403
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#define _ARC_V2_EFA 0x404
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#define _ARC_V2_ERSEC_STAT 0x406
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#define _ARC_V2_ICAUSE 0x40a
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#define _ARC_V2_IRQ_SELECT 0x40b
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#define _ARC_V2_IRQ_ENABLE 0x40c
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#define _ARC_V2_IRQ_TRIGGER 0x40d
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#define _ARC_V2_IRQ_STATUS 0x40f
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#define _ARC_V2_IRQ_PULSE_CANCEL 0x415
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#define _ARC_V2_IRQ_PENDING 0x416
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#define _ARC_V2_FPU_CTRL 0x300
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#define _ARC_V2_FPU_STATUS 0x301
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#define _ARC_V2_FPU_DPFP1L 0x302
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#define _ARC_V2_FPU_DPFP1H 0x303
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#define _ARC_V2_FPU_DPFP2L 0x304
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#define _ARC_V2_FPU_DPFP2H 0x305
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#define _ARC_V2_MPU_EN 0x409
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#define _ARC_V2_MPU_RDB0 0x422
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#define _ARC_V2_MPU_RDP0 0x423
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#define _ARC_V2_MPU_INDEX 0x448
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#define _ARC_V2_MPU_RSTART 0x449
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#define _ARC_V2_MPU_REND 0x44A
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#define _ARC_V2_MPU_RPER 0x44B
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#define _ARC_V2_MPU_PROBE 0x44C
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#define _ARC_V2_ACC0_GHI 0x583
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#define _ARC_V2_ACC0_HI 0x582
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#define _ARC_V2_ACC0_GLO 0x581
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#define _ARC_V2_ACC0_LO 0x580
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#define _ARC_V2_DSP_BUILD 0x7A
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#define _ARC_V2_DSP_CTRL 0x59f
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#define _ARC_V2_DSP_BFLY0 0x598
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#define _ARC_V2_DSP_FFT_CTRL 0x59e
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#define _ARC_V2_AGU_BUILD 0xcc
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#define _ARC_V2_AGU_AP0 0x5c0
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#define _ARC_V2_AGU_AP1 0x5c1
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#define _ARC_V2_AGU_AP2 0x5c2
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#define _ARC_V2_AGU_AP3 0x5c3
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#define _ARC_V2_AGU_AP4 0x5c4
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#define _ARC_V2_AGU_AP5 0x5c5
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#define _ARC_V2_AGU_AP6 0x5c6
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#define _ARC_V2_AGU_AP7 0x5c7
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#define _ARC_V2_AGU_AP8 0x5c8
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#define _ARC_V2_AGU_AP9 0x5c9
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#define _ARC_V2_AGU_AP10 0x5ca
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#define _ARC_V2_AGU_AP11 0x5cb
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#define _ARC_V2_AGU_OS0 0x5d0
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#define _ARC_V2_AGU_OS1 0x5d1
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#define _ARC_V2_AGU_OS2 0x5d2
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#define _ARC_V2_AGU_OS3 0x5d3
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#define _ARC_V2_AGU_OS4 0x5d4
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#define _ARC_V2_AGU_OS5 0x5d5
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#define _ARC_V2_AGU_OS6 0x5d6
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#define _ARC_V2_AGU_OS7 0x5d7
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#define _ARC_V2_AGU_MOD0 0x5e0
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#define _ARC_V2_AGU_MOD1 0x5e1
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#define _ARC_V2_AGU_MOD2 0x5e2
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#define _ARC_V2_AGU_MOD3 0x5e3
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#define _ARC_V2_AGU_MOD4 0x5e4
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#define _ARC_V2_AGU_MOD5 0x5e5
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#define _ARC_V2_AGU_MOD6 0x5e6
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#define _ARC_V2_AGU_MOD7 0x5e7
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#define _ARC_V2_AGU_MOD8 0x5e8
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#define _ARC_V2_AGU_MOD9 0x5e9
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#define _ARC_V2_AGU_MOD10 0x5ea
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#define _ARC_V2_AGU_MOD11 0x5eb
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#define _ARC_V2_AGU_MOD12 0x5ec
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#define _ARC_V2_AGU_MOD13 0x5ed
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#define _ARC_V2_AGU_MOD14 0x5ee
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#define _ARC_V2_AGU_MOD15 0x5ef
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#define _ARC_V2_AGU_MOD16 0x5f0
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#define _ARC_V2_AGU_MOD17 0x5f1
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#define _ARC_V2_AGU_MOD18 0x5f2
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#define _ARC_V2_AGU_MOD19 0x5f3
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#define _ARC_V2_AGU_MOD20 0x5f4
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#define _ARC_V2_AGU_MOD21 0x5f5
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#define _ARC_V2_AGU_MOD22 0x5f6
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#define _ARC_V2_AGU_MOD23 0x5f7
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#define _ARC_HW_PF_BUILD 0xf70
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#define _ARC_HW_PF_CTRL 0x4f
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/* _ARC_HW_PF_CTRL bits */
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#define _ARC_HW_PF_CTRL_ENABLE BIT(0)
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/* STATUS32/STATUS32_P0 bits */
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#define _ARC_V2_STATUS32_H (1 << 0)
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#define Z_ARC_V2_STATUS32_E(x) ((x) << 1)
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#define _ARC_V2_STATUS32_AE_BIT 5
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#define _ARC_V2_STATUS32_AE (1 << _ARC_V2_STATUS32_AE_BIT)
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#define _ARC_V2_STATUS32_DE (1 << 6)
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#define _ARC_V2_STATUS32_U_BIT 7
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#define _ARC_V2_STATUS32_U (1 << _ARC_V2_STATUS32_U_BIT)
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#define _ARC_V2_STATUS32_V (1 << 8)
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#define _ARC_V2_STATUS32_C (1 << 9)
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#define _ARC_V2_STATUS32_N (1 << 10)
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#define _ARC_V2_STATUS32_Z (1 << 11)
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#define _ARC_V2_STATUS32_L (1 << 12)
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#define _ARC_V2_STATUS32_DZ_BIT 13
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#define _ARC_V2_STATUS32_DZ (1 << _ARC_V2_STATUS32_DZ_BIT)
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#define _ARC_V2_STATUS32_SC_BIT 14
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#define _ARC_V2_STATUS32_SC (1 << _ARC_V2_STATUS32_SC_BIT)
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#define _ARC_V2_STATUS32_ES (1 << 15)
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#define _ARC_V2_STATUS32_RB(x) ((x) << 16)
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#define _ARC_V2_STATUS32_AD_BIT 19
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#define _ARC_V2_STATUS32_AD (1 << _ARC_V2_STATUS32_AD_BIT)
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#define _ARC_V2_STATUS32_US_BIT 20
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#define _ARC_V2_STATUS32_US (1 << _ARC_V2_STATUS32_US_BIT)
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#define _ARC_V2_STATUS32_S_BIT 21
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#define _ARC_V2_STATUS32_S (1 << _ARC_V2_STATUS32_US_BIT)
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#define _ARC_V2_STATUS32_IE (1 << 31)
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/* SEC_STAT bits */
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#define _ARC_V2_SEC_STAT_SSC_BIT 0
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#define _ARC_V2_SEC_STAT_SSC (1 << _ARC_V2_SEC_STAT_SSC_BIT)
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#define _ARC_V2_SEC_STAT_NSRT_BIT 1
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#define _ARC_V2_SEC_STAT_NSRT (1 << _ARC_V2_SEC_STAT_NSRT_BIT)
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#define _ARC_V2_SEC_STAT_NSRU_BIT 2
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#define _ARC_V2_SEC_STAT_NSRU (1 << _ARC_V2_SEC_STAT_NSRU_BIT)
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#define _ARC_V2_SEC_STAT_IRM_BIT 3
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#define _ARC_V2_SEC_STAT_IRM (1 << _ARC_V2_SEC_STAT_IRM_BIT)
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#define _ARC_V2_SEC_STAT_SUE_BIT 4
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#define _ARC_V2_SEC_STAT_SUE (1 << _ARC_V2_SEC_STAT_SUE_BIT)
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#define _ARC_V2_SEC_STAT_NIC_BIT 5
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#define _ARC_V2_SEC_STAT_NIC (1 << _ARC_V2_SEC_STAT_NIC_BIT)
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/* interrupt related bits */
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#define _ARC_V2_IRQ_PRIORITY_SECURE 0x100
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/* exception cause register masks */
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#define Z_ARC_V2_ECR_VECTOR(X) ((X & 0xff0000) >> 16)
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#define Z_ARC_V2_ECR_CODE(X) ((X & 0xff00) >> 8)
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#define Z_ARC_V2_ECR_PARAMETER(X) (X & 0xff)
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#ifndef _ASMLANGUAGE
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#include <
zephyr/types.h
>
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#if defined(__CCAC__)
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#define z_arc_v2_aux_reg_read(reg) _lr((volatile uint32_t)reg)
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#define z_arc_v2_aux_reg_write(reg, val) \
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_sr((unsigned int)val, (volatile uint32_t)reg)
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#else
/* ! __CCAC__ */
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#define z_arc_v2_aux_reg_read(reg) __builtin_arc_lr((volatile uint32_t)reg)
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#define z_arc_v2_aux_reg_write(reg, val) \
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__builtin_arc_sr((unsigned int)val, (volatile uint32_t)reg)
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#endif
/* __CCAC__ */
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#endif
/* _ASMLANGUAGE */
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#define z_arc_v2_core_id() \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__("lr %0, [%1]\n" \
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"xbfu %0, %0, 0xe8\n" \
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: "=r"(__ret) \
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: "i"(_ARC_V2_IDENTITY)); \
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__ret; \
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})
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#endif
/* ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_ */
types.h
util_macro.h
Macro utilities.
zephyr
arch
arc
v2
aux_regs.h
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