Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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cache.h
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1/*
2 * Copyright (c) 2015 Wind River Systems, Inc.
3 * Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_CACHE_H_
9#define ZEPHYR_INCLUDE_CACHE_H_
10
15
16#include <zephyr/kernel.h>
17#include <zephyr/arch/cpu.h>
18#include <zephyr/debug/sparse.h>
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#if defined(CONFIG_EXTERNAL_CACHE)
26
27#elif defined(CONFIG_ARCH_CACHE)
28#include <zephyr/arch/cache.h>
29
30#elif defined(CONFIG_SOC_CACHE)
31#include <soc_cache.h>
32
33#endif
34
40
48{
49#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
51#endif
52}
53
61{
62#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
64#endif
65}
66
74{
75#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
77#endif
78}
79
87{
88#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
90#endif
91}
92
103{
104#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
105 return cache_data_flush_all();
106#endif
107 return -ENOTSUP;
108}
109
120{
121#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
122 return cache_instr_flush_all();
123#endif
124 return -ENOTSUP;
125}
126
137{
138#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
139 return cache_data_invd_all();
140#endif
141 return -ENOTSUP;
142}
143
154{
155#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
156 return cache_instr_invd_all();
157#endif
158 return -ENOTSUP;
159}
160
171{
172#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
174#endif
175 return -ENOTSUP;
176}
177
188{
189#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
191#endif
192 return -ENOTSUP;
193}
194
214__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
215
216static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
217{
218#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
219 return cache_data_flush_range(addr, size);
220#endif
221 ARG_UNUSED(addr);
222 ARG_UNUSED(size);
223
224 return -ENOTSUP;
225}
226
246static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
247{
248#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
249 return cache_instr_flush_range(addr, size);
250#endif
251 ARG_UNUSED(addr);
252 ARG_UNUSED(size);
253
254 return -ENOTSUP;
255}
256
277__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
278
279static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
280{
281#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
282 return cache_data_invd_range(addr, size);
283#endif
284 ARG_UNUSED(addr);
285 ARG_UNUSED(size);
286
287 return -ENOTSUP;
288}
289
310static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
311{
312#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
313 return cache_instr_invd_range(addr, size);
314#endif
315 ARG_UNUSED(addr);
316 ARG_UNUSED(size);
317
318 return -ENOTSUP;
319}
320
341__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
342
343static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
344{
345#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
346 return cache_data_flush_and_invd_range(addr, size);
347#endif
348 ARG_UNUSED(addr);
349 ARG_UNUSED(size);
350
351 return -ENOTSUP;
352}
353
374static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
375{
376#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
377 return cache_instr_flush_and_invd_range(addr, size);
378#endif
379 ARG_UNUSED(addr);
380 ARG_UNUSED(size);
381
382 return -ENOTSUP;
383}
384
401{
402#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
404#elif defined(CONFIG_DCACHE_LINE_SIZE)
405 return CONFIG_DCACHE_LINE_SIZE;
406#else
407 return 0;
408#endif
409}
410
427{
428#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
430#elif defined(CONFIG_ICACHE_LINE_SIZE)
431 return CONFIG_ICACHE_LINE_SIZE;
432#else
433 return 0;
434#endif
435}
436
451{
452#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
453 return cache_is_ptr_cached(ptr);
454#else
455 ARG_UNUSED(ptr);
456
457 return false;
458#endif
459}
460
475{
476#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
477 return cache_is_ptr_uncached(ptr);
478#else
479 ARG_UNUSED(ptr);
480
481 return false;
482#endif
483}
484
503static ALWAYS_INLINE void __sparse_cache *sys_cache_cached_ptr_get(void *ptr)
504{
505#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
506 return cache_cached_ptr(ptr);
507#else
508 return (__sparse_force void __sparse_cache *)ptr;
509#endif
510}
511
528static ALWAYS_INLINE void *sys_cache_uncached_ptr_get(void __sparse_cache *ptr)
529{
530#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS)
531 return cache_uncached_ptr(ptr);
532#else
533 return (__sparse_force void *)ptr;
534#endif
535}
536
537
538#ifdef CONFIG_LIBMETAL
539static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
540{
541 sys_cache_data_flush_range(addr, size);
542}
543#endif
544
545#if defined(CONFIG_CACHE_CAN_SAY_MEM_COHERENCE) || defined(__DOXYGEN__)
564{
565 return cache_is_mem_coherent(ptr);
566}
567#endif /* CONFIG_CACHE_CAN_SAY_MEM_COHERENCE */
568
569#include <zephyr/syscalls/cache.h>
570#ifdef __cplusplus
571}
572#endif
573
577
578#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
Public APIs for architectural cache controller drivers.
Main header file for external cache controller driver API.
#define cache_uncached_ptr(ptr)
Definition cache.h:351
#define cache_instr_invd_all
Definition cache.h:229
#define cache_cached_ptr(ptr)
Definition cache.h:348
#define cache_instr_disable
Definition cache.h:203
#define cache_is_ptr_uncached(ptr)
Definition cache.h:345
#define cache_instr_flush_all
Definition cache.h:216
#define cache_data_flush_and_invd_range(addr, size)
Definition cache.h:159
#define cache_instr_invd_range(addr, size)
Definition cache.h:289
#define cache_instr_flush_and_invd_all
Definition cache.h:242
#define cache_instr_enable
Definition cache.h:194
#define cache_instr_flush_range(addr, size)
Definition cache.h:265
#define cache_data_invd_range(addr, size)
Definition cache.h:134
#define cache_instr_flush_and_invd_range(addr, size)
Definition cache.h:313
#define cache_data_invd_all
Definition cache.h:74
#define cache_is_mem_coherent(ptr)
Definition cache.h:358
#define cache_is_ptr_cached(ptr)
Definition cache.h:342
#define cache_data_flush_range(addr, size)
Definition cache.h:110
#define cache_data_flush_and_invd_all
Definition cache.h:87
#define cache_data_flush_all
Definition cache.h:61
#define cache_data_enable
Definition cache.h:39
#define cache_instr_line_size_get
Definition cache.h:334
#define cache_data_disable
Definition cache.h:48
#define cache_data_line_size_get
Definition cache.h:179
static ALWAYS_INLINE bool sys_cache_is_ptr_cached(void *ptr)
Test if a pointer is in cached region.
Definition cache.h:450
static ALWAYS_INLINE void * sys_cache_uncached_ptr_get(void *ptr)
Return uncached pointer to a RAM address.
Definition cache.h:528
static ALWAYS_INLINE bool sys_cache_is_mem_coherent(void *ptr)
Detect memory coherence type.
Definition cache.h:563
static ALWAYS_INLINE int sys_cache_data_flush_all(void)
Flush the d-cache.
Definition cache.h:102
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
Flush and Invalidate the i-cache.
Definition cache.h:187
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
Get the i-cache line size.
Definition cache.h:426
static ALWAYS_INLINE void sys_cache_instr_disable(void)
Disable the i-cache.
Definition cache.h:86
int sys_cache_data_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the d-cache.
int sys_cache_data_invd_range(void *addr, size_t size)
Invalidate an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
Flush an address range in the i-cache.
Definition cache.h:246
static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
Flush the i-cache.
Definition cache.h:119
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
Get the d-cache line size.
Definition cache.h:400
int sys_cache_data_flush_range(void *addr, size_t size)
Flush an address range in the d-cache.
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
Flush and Invalidate an address range in the i-cache.
Definition cache.h:374
static ALWAYS_INLINE void * sys_cache_cached_ptr_get(void *ptr)
Return cached pointer to a RAM address.
Definition cache.h:503
static ALWAYS_INLINE void sys_cache_data_disable(void)
Disable the d-cache.
Definition cache.h:60
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
Invalidate an address range in the i-cache.
Definition cache.h:310
static ALWAYS_INLINE void sys_cache_data_enable(void)
Enable the d-cache.
Definition cache.h:47
static ALWAYS_INLINE void sys_cache_instr_enable(void)
Enable the i-cache.
Definition cache.h:73
static ALWAYS_INLINE int sys_cache_data_invd_all(void)
Invalidate the d-cache.
Definition cache.h:136
static ALWAYS_INLINE bool sys_cache_is_ptr_uncached(void *ptr)
Test if a pointer is in un-cached region.
Definition cache.h:474
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
Flush and Invalidate the d-cache.
Definition cache.h:170
static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
Invalidate the i-cache.
Definition cache.h:153
#define ENOTSUP
Unsupported value.
Definition errno.h:114
#define ALWAYS_INLINE
Definition common.h:160
Public kernel APIs.