Zephyr API Documentation 4.5.0-rc1
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clock_control_ifx_cat1.h
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1/*
2 * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_IFX_CAT1_H_
9#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_IFX_CAT1_H_
10
16
17#include <cy_sysclk.h>
18#include <cy_systick.h>
19
25
27
28#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
29
30#if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
31/* Converts the group/div pair into a unique block number. */
32#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
33
34#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
35 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
36 (gr), CY_SYSCLK_DIV_8_BIT), \
37 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
38 (gr), CY_SYSCLK_DIV_16_BIT), \
39 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
40 (gr), CY_SYSCLK_DIV_16_5_BIT), \
41 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
42 (gr), CY_SYSCLK_DIV_24_5_BIT)
43#else
44/* Converts the group/div pair into a unique block number. */
45#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \
46 (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div))
47#define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR)
48#define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \
49 ((clock >> 2) - \
50 (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR))
51
52#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \
53 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \
54 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \
55 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \
56 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \
57 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \
58 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \
59 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \
60 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT)
61#endif
62
64
67#define CLK_HF0 (0U)
68#define CLK_HF1 (1U)
69#define CLK_HF2 (2U)
70#define CLK_HF3 (3U)
71#define CLK_HF4 (4U)
72#define CLK_HF5 (5U)
73#define CLK_HF6 (6U)
74#define CLK_HF7 (7U)
75#define CLK_HF8 (8U)
76#define CLK_HF9 (9U)
77#define CLK_HF10 (10U)
78#define CLK_HF11 (11U)
79#define CLK_HF12 (12U)
80#define CLK_HF13 (13U)
82
84enum ifx_cat1_clock_block {
85#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
86 /* The first four items are here for backwards compatibility with old clock APIs */
87 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT,
88 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
89 CY_SYSCLK_DIV_16_BIT,
90 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
91 CY_SYSCLK_DIV_16_5_BIT,
92 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
93 CY_SYSCLK_DIV_24_5_BIT,
94
95 IFX_CAT1_CLOCK_BLOCK_IMO,
96 IFX_CAT1_CLOCK_BLOCK_ECO,
97 IFX_CAT1_CLOCK_BLOCK_EXT,
98 IFX_CAT1_CLOCK_BLOCK_ALTHF,
99 IFX_CAT1_CLOCK_BLOCK_ALTLF,
100 IFX_CAT1_CLOCK_BLOCK_ILO,
101#if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
102 IFX_CAT1_CLOCK_BLOCK_PILO,
103#endif
104
105 IFX_CAT1_CLOCK_BLOCK_WCO,
106 IFX_CAT1_CLOCK_BLOCK_MFO,
107
108 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
109
110 IFX_CAT1_CLOCK_BLOCK_FLL,
111#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
112 IFX_CAT1_CLOCK_BLOCK_PLL200,
113 IFX_CAT1_CLOCK_BLOCK_PLL400,
114#else
115 IFX_CAT1_CLOCK_BLOCK_PLL,
116#endif
117
118 IFX_CAT1_CLOCK_BLOCK_LF,
119 IFX_CAT1_CLOCK_BLOCK_MF,
120 IFX_CAT1_CLOCK_BLOCK_HF,
121
122 IFX_CAT1_CLOCK_BLOCK_PUMP,
123 IFX_CAT1_CLOCK_BLOCK_BAK,
124 IFX_CAT1_CLOCK_BLOCK_TIMER,
125 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
126
127 IFX_CAT1_CLOCK_BLOCK_FAST,
128 IFX_CAT1_CLOCK_BLOCK_PERI,
129 IFX_CAT1_CLOCK_BLOCK_SLOW,
130
131#elif defined(COMPONENT_CAT1B)
132
133 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
134 CY_SYSCLK_DIV_8_BIT,
135 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
136 CY_SYSCLK_DIV_16_BIT,
137 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
138 CY_SYSCLK_DIV_16_5_BIT,
140 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
141 CY_SYSCLK_DIV_24_5_BIT,
143
144/* The first four items are here for backwards compatibility with old clock APIs */
145#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
146 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
147#endif
148#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
149 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
150#endif
151#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
152 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
153#endif
154#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
155 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
156#endif
157#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
158 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
159#endif
160#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
161 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
162#endif
163#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
164 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
165#endif
166#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
167 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
168#endif
169#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
170 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
171#endif
172#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
173 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
174#endif
175#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
176 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
177#endif
178#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
179 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
180#endif
181#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
182 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
183#endif
184#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
185 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
186#endif
187#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
188 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
189#endif
190#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
191 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
192#endif
193
194 IFX_CAT1_CLOCK_BLOCK_IHO,
195 IFX_CAT1_CLOCK_BLOCK_IMO,
196 IFX_CAT1_CLOCK_BLOCK_ECO,
197 IFX_CAT1_CLOCK_BLOCK_EXT,
198 IFX_CAT1_CLOCK_BLOCK_ALTHF,
199 IFX_CAT1_CLOCK_BLOCK_ALTLF,
200 IFX_CAT1_CLOCK_BLOCK_ILO,
201 IFX_CAT1_CLOCK_BLOCK_PILO,
202 IFX_CAT1_CLOCK_BLOCK_WCO,
203 IFX_CAT1_CLOCK_BLOCK_MFO,
204
205 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
206
207 IFX_CAT1_CLOCK_BLOCK_FLL,
208 IFX_CAT1_CLOCK_BLOCK_PLL200,
209 IFX_CAT1_CLOCK_BLOCK_PLL400,
210 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
211
212 IFX_CAT1_CLOCK_BLOCK_LF,
213 IFX_CAT1_CLOCK_BLOCK_MF,
214 IFX_CAT1_CLOCK_BLOCK_HF,
215
216 IFX_CAT1_CLOCK_BLOCK_PUMP,
217 IFX_CAT1_CLOCK_BLOCK_BAK,
218 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
219 IFX_CAT1_CLOCK_BLOCK_PERI,
220
221#elif defined(COMPONENT_CAT1C)
222
223 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
224 CY_SYSCLK_DIV_8_BIT,
225 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
226 CY_SYSCLK_DIV_16_BIT,
227 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
228 CY_SYSCLK_DIV_16_5_BIT,
230 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
231 CY_SYSCLK_DIV_24_5_BIT,
233
234/* The first four items are here for backwards compatibility with old clock APIs */
235#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
236 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
237#endif
238#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
239 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
240#endif
241#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
242 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
243#endif
244#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
245 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
246#endif
247#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
248 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
249#endif
250#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
251 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
252#endif
253#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
254 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
255#endif
256#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
257 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
258#endif
259#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
260 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
261#endif
262#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
263 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
264#endif
265#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
266 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
267#endif
268#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
269 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
270#endif
271#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
272 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
273#endif
274#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
275 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
276#endif
277#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
278 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
279#endif
280#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
281 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
282#endif
283
284 IFX_CAT1_CLOCK_BLOCK_IMO,
285 IFX_CAT1_CLOCK_BLOCK_ECO,
286 IFX_CAT1_CLOCK_BLOCK_EXT,
287 IFX_CAT1_CLOCK_BLOCK_ILO,
288 IFX_CAT1_CLOCK_BLOCK_WCO,
289
290 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
291
292 IFX_CAT1_CLOCK_BLOCK_FLL,
293 IFX_CAT1_CLOCK_BLOCK_PLL200,
294 IFX_CAT1_CLOCK_BLOCK_PLL400,
295
296 IFX_CAT1_CLOCK_BLOCK_LF,
297 IFX_CAT1_CLOCK_BLOCK_HF,
298 IFX_CAT1_CLOCK_BLOCK_BAK,
299 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
300
301 IFX_CAT1_CLOCK_BLOCK_PERI,
302 IFX_CAT1_CLOCK_BLOCK_FAST,
303 IFX_CAT1_CLOCK_BLOCK_SLOW,
304 IFX_CAT1_CLOCK_BLOCK_MEM,
305 IFX_CAT1_CLOCK_BLOCK_TIMER,
306#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
307
308 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
309 CY_SYSCLK_DIV_8_BIT,
310 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
311 CY_SYSCLK_DIV_16_BIT,
312 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
313 CY_SYSCLK_DIV_16_5_BIT,
315 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
316 CY_SYSCLK_DIV_24_5_BIT,
318
319#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1)
320 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0),
321#endif
322#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2)
323 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1),
324#endif
325#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3)
326 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2),
327#endif
328#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4)
329 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3),
330#endif
331#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5)
332 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4),
333#endif
334#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6)
335 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5),
336#endif
337#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7)
338 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6),
339#endif
340#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8)
341 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7),
342#endif
343#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9)
344 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8),
345#endif
346#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10)
347 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9),
348#endif
349#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11)
350#warning "Unhandled PERI0 PCLK number"
351#endif
352
353#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1)
354 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0),
355#endif
356#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2)
357 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1),
358#endif
359#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3)
360 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2),
361#endif
362#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4)
363 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3),
364#endif
365#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5)
366 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4),
367#endif
368#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6)
369 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5),
370#endif
371#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7)
372#warning "Unhandled PERI1 PCLK number"
373#endif
374
375 IFX_CAT1_CLOCK_BLOCK_IHO,
376 IFX_CAT1_CLOCK_BLOCK_ECO,
377 IFX_CAT1_CLOCK_BLOCK_EXT,
378 IFX_CAT1_CLOCK_BLOCK_PILO,
379 IFX_CAT1_CLOCK_BLOCK_WCO,
380
381 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
382
383 IFX_CAT1_CLOCK_BLOCK_DPLL250,
384 IFX_CAT1_CLOCK_BLOCK_DPLL500,
385 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
386
387 IFX_CAT1_CLOCK_BLOCK_LF,
388 IFX_CAT1_CLOCK_BLOCK_MF,
389 IFX_CAT1_CLOCK_BLOCK_HF,
390
391 IFX_CAT1_CLOCK_BLOCK_BAK,
392 IFX_CAT1_CLOCK_BLOCK_PERI,
393
394#elif defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
395 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
396 CY_SYSCLK_DIV_16_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
397
398 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
399 CY_SYSCLK_DIV_16_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */
400
401 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
402 CY_SYSCLK_DIV_24_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */
403#endif
404};
405
415
426
436int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
437
445static inline uint32_t
446ifx_cat1_utils_peri_pclk_get_frequency(en_clk_dst_t clk_dest,
447 const struct ifx_cat1_clock *peri_clock)
448{
449#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
450 return Cy_SysClk_PeriPclkGetFrequency(
451 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
452 peri_clock->channel);
453#else
454 CY_UNUSED_PARAMETER(clk_dest);
455 return Cy_SysClk_PeriphGetFrequency(
456 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel);
457#endif
458}
459
467static inline cy_rslt_t
468ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
469 const struct ifx_cat1_clock *peri_clock)
470{
471#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
472 return Cy_SysClk_PeriPclkEnableDivider(
473 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
474 peri_clock->channel);
475#else
476 CY_UNUSED_PARAMETER(clk_dest);
477 return Cy_SysClk_PeriphEnableDivider(
478 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel);
479#endif
480}
481
489static inline cy_rslt_t
490ifx_cat1_utils_peri_pclk_disable_divider(en_clk_dst_t clk_dest,
491 const struct ifx_cat1_clock *peri_clock)
492{
493#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
494 return Cy_SysClk_PeriPclkDisableDivider(
495 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
496 peri_clock->channel);
497#else
498 CY_UNUSED_PARAMETER(clk_dest);
499 return Cy_SysClk_PeriphDisableDivider(
500 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel);
501#endif
502}
503
515static inline bool ifx_cat1_utils_peri_is_fract_div(const struct ifx_cat1_clock *peri_clock)
516{
517 cy_en_divider_types_t type =
518 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block);
519
520 return (type == CY_SYSCLK_DIV_16_5_BIT) || (type == CY_SYSCLK_DIV_24_5_BIT);
521}
522
531static inline cy_rslt_t
532ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
533 const struct ifx_cat1_clock *peri_clock, uint32_t div)
534{
535#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
536 return Cy_SysClk_PeriPclkSetDivider(
537 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
538 peri_clock->channel, div);
539#else
540 CY_UNUSED_PARAMETER(clk_dest);
541 return Cy_SysClk_PeriphSetDivider(
542 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel,
543 div);
544#endif
545}
546
556static inline cy_rslt_t
557ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
558 const struct ifx_cat1_clock *peri_clock, uint32_t div_int,
559 uint32_t div_frac)
560{
561#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
562 return Cy_SysClk_PeriPclkSetFracDivider(
563 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
564 peri_clock->channel, div_int, div_frac);
565#else
566 CY_UNUSED_PARAMETER(clk_dest);
567 return Cy_SysClk_PeriphSetFracDivider(
568 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel,
569 div_int, div_frac);
570#endif
571}
572
580static inline uint32_t ifx_cat1_utils_peri_pclk_get_divider(en_clk_dst_t clk_dest,
581 const struct ifx_cat1_clock *peri_clock)
582{
583#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
584 return Cy_SysClk_PeriPclkGetDivider(
585 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
586 peri_clock->channel);
587#else
588 CY_UNUSED_PARAMETER(clk_dest);
589 return Cy_SysClk_PeriphGetDivider(
590 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel);
591#endif
592}
593
602static inline void
603ifx_cat1_utils_peri_pclk_get_frac_divider(en_clk_dst_t clk_dest,
604 const struct ifx_cat1_clock *peri_clock,
605 uint32_t *div_int, uint32_t *div_frac)
606{
607#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
608 Cy_SysClk_PeriPclkGetFracDivider(
609 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
610 peri_clock->channel, div_int, div_frac);
611#else
612 CY_UNUSED_PARAMETER(clk_dest);
613 Cy_SysClk_PeriphGetFracDivider(
614 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block), peri_clock->channel,
615 div_int, div_frac);
616#endif
617}
618
626static inline cy_rslt_t
627ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
628 const struct ifx_cat1_clock *peri_clock)
629{
630#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
631 return Cy_SysClk_PeriPclkAssignDivider(
632 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
633 peri_clock->channel);
634#else
635 return Cy_SysClk_PeriphAssignDivider(
636 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(peri_clock->block),
637 peri_clock->channel);
638#endif
639}
640
641#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
649#define IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(instance, group) (((instance) << 4) | (group))
650
660static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
661{
662 switch (peri_group) {
663 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 0):
664 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 4):
665 return CLK_HF0;
666 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 7):
667 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 0):
668 return CLK_HF1;
669 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 3):
670 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 2):
671 return CLK_HF5;
672 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 4):
673 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 3):
674 return CLK_HF6;
675 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 1):
676 return CLK_HF7;
677 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 2):
678 return CLK_HF9;
679 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 1):
680 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 5):
681 return CLK_HF10;
682 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 8):
683 return CLK_HF11;
684 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 6):
685 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 9):
686 return CLK_HF13;
687 default:
688 break;
689 }
690 return -EINVAL;
691}
692
693#elif defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
703static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
704{
705 switch (peri_group) {
706 case 0:
707 case 2:
708 return CLK_HF0;
709 case 1:
710 case 3:
711 return CLK_HF1;
712 case 4:
713 return CLK_HF2;
714 case 5:
715 return CLK_HF3;
716 case 6:
717 return CLK_HF4;
718 default:
719 break;
720 }
721 return -EINVAL;
722}
723
724#else /* !CONFIG_SOC_FAMILY_INFINEON_EDGE && !CONFIG_SOC_FAMILY_INFINEON_CAT1B */
734static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
735{
736 ARG_UNUSED(peri_group);
737
738 return -EINVAL;
739}
740#endif
741
743
744#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_CLOCK_CONTROL_IFX_CAT1_H_ */
ifx_cat1_utils_peri_pclk_get_frequency
static uint32_t ifx_cat1_utils_peri_pclk_get_frequency(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock)
Get the frequency of a peripheral clock divider.
Definition clock_control_ifx_cat1.h:446
ifx_cat1_clock_control_get_frequency
int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency)
Get the frequency of a clock identified by its Devicetree ordinal.
CLK_HF4
#define CLK_HF4
HF clock 4.
Definition clock_control_ifx_cat1.h:71
ifx_cat1_utils_peri_pclk_get_frac_divider
static void ifx_cat1_utils_peri_pclk_get_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock, uint32_t *div_int, uint32_t *div_frac)
Get the fractional divider value of a peripheral clock.
Definition clock_control_ifx_cat1.h:603
ifx_cat1_utils_peri_pclk_set_frac_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock, uint32_t div_int, uint32_t div_frac)
Set the fractional divider for a peripheral clock.
Definition clock_control_ifx_cat1.h:557
CLK_HF9
#define CLK_HF9
HF clock 9.
Definition clock_control_ifx_cat1.h:76
CLK_HF13
#define CLK_HF13
HF clock 13.
Definition clock_control_ifx_cat1.h:80
CLK_HF5
#define CLK_HF5
HF clock 5.
Definition clock_control_ifx_cat1.h:72
CLK_HF3
#define CLK_HF3
HF clock 3.
Definition clock_control_ifx_cat1.h:70
ifx_cat1_utils_peri_pclk_disable_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_disable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock)
Disable the divider associated with a peripheral clock.
Definition clock_control_ifx_cat1.h:490
CLK_HF10
#define CLK_HF10
HF clock 10.
Definition clock_control_ifx_cat1.h:77
CLK_HF0
#define CLK_HF0
HF clock 0.
Definition clock_control_ifx_cat1.h:67
ifx_cat1_utils_peri_pclk_set_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock, uint32_t div)
Set the integer divider for a peripheral clock.
Definition clock_control_ifx_cat1.h:532
ifx_cat1_utils_peri_pclk_assign_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock)
Assign a divider to a peripheral clock destination.
Definition clock_control_ifx_cat1.h:627
CLK_HF2
#define CLK_HF2
HF clock 2.
Definition clock_control_ifx_cat1.h:69
ifx_cat1_clock_block
ifx_cat1_clock_block
CAT1 clock block (source or domain) selector.
Definition clock_control_ifx_cat1.h:84
CLK_HF1
#define CLK_HF1
HF clock 1.
Definition clock_control_ifx_cat1.h:68
ifx_cat1_utils_peri_is_fract_div
static bool ifx_cat1_utils_peri_is_fract_div(const struct ifx_cat1_clock *peri_clock)
Test whether a peripheral clock uses a fractional (x.5-bit) divider.
Definition clock_control_ifx_cat1.h:515
CLK_HF6
#define CLK_HF6
HF clock 6.
Definition clock_control_ifx_cat1.h:73
ifx_cat1_utils_peri_pclk_enable_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock)
Enable the divider associated with a peripheral clock.
Definition clock_control_ifx_cat1.h:468
CLK_HF7
#define CLK_HF7
HF clock 7.
Definition clock_control_ifx_cat1.h:74
CLK_HF11
#define CLK_HF11
HF clock 11.
Definition clock_control_ifx_cat1.h:78
ifx_cat1_utils_peri_pclk_get_hfclk
static uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
Map a peripheral group index to the HF clock that sources it.
Definition clock_control_ifx_cat1.h:734
ifx_cat1_utils_peri_pclk_get_divider
static uint32_t ifx_cat1_utils_peri_pclk_get_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *peri_clock)
Get the integer divider value of a peripheral clock.
Definition clock_control_ifx_cat1.h:580
EINVAL
#define EINVAL
Invalid argument.
Definition errno.h:61
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
ifx_cat1_clock
CAT1 clock descriptor.
Definition clock_control_ifx_cat1.h:407
ifx_cat1_clock::group
uint8_t group
Peripheral clock group number.
Definition clock_control_ifx_cat1.h:411
ifx_cat1_clock::instance
uint8_t instance
Peripheral clock instance number.
Definition clock_control_ifx_cat1.h:410
ifx_cat1_clock::funcs
const void * funcs
Clock-specific functions.
Definition clock_control_ifx_cat1.h:413
ifx_cat1_clock::channel
uint8_t channel
Clock channel number.
Definition clock_control_ifx_cat1.h:409
ifx_cat1_clock::block
enum ifx_cat1_clock_block block
Clock block type.
Definition clock_control_ifx_cat1.h:408
ifx_cat1_clock::reserved
bool reserved
Reserved for future use.
Definition clock_control_ifx_cat1.h:412
ifx_cat1_resource_inst
CAT1 resource instance descriptor.
Definition clock_control_ifx_cat1.h:417
ifx_cat1_resource_inst::block_num
uint8_t block_num
The resource block index.
Definition clock_control_ifx_cat1.h:419
ifx_cat1_resource_inst::type
uint8_t type
The resource block type.
Definition clock_control_ifx_cat1.h:418
ifx_cat1_resource_inst::channel_num
uint8_t channel_num
The channel number, if the resource type defines multiple channels per block instance.
Definition clock_control_ifx_cat1.h:424