Zephyr API Documentation 4.3.0-rc2
A Scalable Open Source RTOS
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clock_control_ifx_cat1.h
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1/*
2 * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <cy_sysclk.h>
9#include <cy_systick.h>
10
11#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
12
13#if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
14/* Converts the group/div pair into a unique block number. */
15#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
16
17#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
18 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
19 (gr), CY_SYSCLK_DIV_8_BIT), \
20 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
21 (gr), CY_SYSCLK_DIV_16_BIT), \
22 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
23 (gr), CY_SYSCLK_DIV_16_5_BIT), \
24 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
25 (gr), CY_SYSCLK_DIV_24_5_BIT)
26#else
27/* Converts the group/div pair into a unique block number. */
28#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \
29 (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div))
30#define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR)
31#define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \
32 ((clock >> 2) - \
33 (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR))
34
35#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \
36 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \
37 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \
38 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \
39 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \
40 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \
41 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \
42 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \
43 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT)
44#endif
45
46/* High frequency clock indices. */
47#define CLK_HF0 (0U)
48#define CLK_HF1 (1U)
49#define CLK_HF2 (2U)
50#define CLK_HF3 (3U)
51#define CLK_HF4 (4U)
52#define CLK_HF5 (5U)
53#define CLK_HF6 (6U)
54#define CLK_HF7 (7U)
55#define CLK_HF8 (8U)
56#define CLK_HF9 (9U)
57#define CLK_HF10 (10U)
58#define CLK_HF11 (11U)
59#define CLK_HF12 (12U)
60#define CLK_HF13 (13U)
61
62enum ifx_cat1_clock_block {
63#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
64 /* The first four items are here for backwards compatibility with old clock APIs */
65 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT,
66 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
67 CY_SYSCLK_DIV_16_BIT,
68 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
69 CY_SYSCLK_DIV_16_5_BIT,
70 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
71 CY_SYSCLK_DIV_24_5_BIT,
72
73 IFX_CAT1_CLOCK_BLOCK_IMO,
74 IFX_CAT1_CLOCK_BLOCK_ECO,
75 IFX_CAT1_CLOCK_BLOCK_EXT,
76 IFX_CAT1_CLOCK_BLOCK_ALTHF,
77 IFX_CAT1_CLOCK_BLOCK_ALTLF,
78 IFX_CAT1_CLOCK_BLOCK_ILO,
79#if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
80 IFX_CAT1_CLOCK_BLOCK_PILO,
81#endif
82
83 IFX_CAT1_CLOCK_BLOCK_WCO,
84 IFX_CAT1_CLOCK_BLOCK_MFO,
85
86 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
87
88 IFX_CAT1_CLOCK_BLOCK_FLL,
89#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
90 IFX_CAT1_CLOCK_BLOCK_PLL200,
91 IFX_CAT1_CLOCK_BLOCK_PLL400,
92#else
93 IFX_CAT1_CLOCK_BLOCK_PLL,
94#endif
95
96 IFX_CAT1_CLOCK_BLOCK_LF,
97 IFX_CAT1_CLOCK_BLOCK_MF,
98 IFX_CAT1_CLOCK_BLOCK_HF,
99
100 IFX_CAT1_CLOCK_BLOCK_PUMP,
101 IFX_CAT1_CLOCK_BLOCK_BAK,
102 IFX_CAT1_CLOCK_BLOCK_TIMER,
103 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
104
105 IFX_CAT1_CLOCK_BLOCK_FAST,
106 IFX_CAT1_CLOCK_BLOCK_PERI,
107 IFX_CAT1_CLOCK_BLOCK_SLOW,
108
109#elif defined(COMPONENT_CAT1B)
110
111 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
112 CY_SYSCLK_DIV_8_BIT,
113 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
114 CY_SYSCLK_DIV_16_BIT,
115 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
116 CY_SYSCLK_DIV_16_5_BIT,
118 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
119 CY_SYSCLK_DIV_24_5_BIT,
121
122/* The first four items are here for backwards compatibility with old clock APIs */
123#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
124 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
125#endif
126#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
127 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
128#endif
129#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
130 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
131#endif
132#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
133 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
134#endif
135#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
136 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
137#endif
138#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
139 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
140#endif
141#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
142 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
143#endif
144#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
145 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
146#endif
147#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
148 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
149#endif
150#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
151 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
152#endif
153#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
154 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
155#endif
156#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
157 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
158#endif
159#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
160 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
161#endif
162#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
163 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
164#endif
165#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
166 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
167#endif
168#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
169 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
170#endif
171
172 IFX_CAT1_CLOCK_BLOCK_IHO,
173 IFX_CAT1_CLOCK_BLOCK_IMO,
174 IFX_CAT1_CLOCK_BLOCK_ECO,
175 IFX_CAT1_CLOCK_BLOCK_EXT,
176 IFX_CAT1_CLOCK_BLOCK_ALTHF,
177 IFX_CAT1_CLOCK_BLOCK_ALTLF,
178 IFX_CAT1_CLOCK_BLOCK_ILO,
179 IFX_CAT1_CLOCK_BLOCK_PILO,
180 IFX_CAT1_CLOCK_BLOCK_WCO,
181 IFX_CAT1_CLOCK_BLOCK_MFO,
182
183 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
184
185 IFX_CAT1_CLOCK_BLOCK_FLL,
186 IFX_CAT1_CLOCK_BLOCK_PLL200,
187 IFX_CAT1_CLOCK_BLOCK_PLL400,
188 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
189
190 IFX_CAT1_CLOCK_BLOCK_LF,
191 IFX_CAT1_CLOCK_BLOCK_MF,
192 IFX_CAT1_CLOCK_BLOCK_HF,
193
194 IFX_CAT1_CLOCK_BLOCK_PUMP,
195 IFX_CAT1_CLOCK_BLOCK_BAK,
196 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
197 IFX_CAT1_CLOCK_BLOCK_PERI,
198
199#elif defined(COMPONENT_CAT1C)
200
201 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
202 CY_SYSCLK_DIV_8_BIT,
203 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
204 CY_SYSCLK_DIV_16_BIT,
205 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
206 CY_SYSCLK_DIV_16_5_BIT,
208 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
209 CY_SYSCLK_DIV_24_5_BIT,
211
212/* The first four items are here for backwards compatibility with old clock APIs */
213#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
214 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
215#endif
216#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
217 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
218#endif
219#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
220 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
221#endif
222#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
223 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
224#endif
225#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
226 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
227#endif
228#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
229 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
230#endif
231#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
232 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
233#endif
234#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
235 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
236#endif
237#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
238 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
239#endif
240#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
241 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
242#endif
243#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
244 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
245#endif
246#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
247 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
248#endif
249#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
250 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
251#endif
252#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
253 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
254#endif
255#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
256 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
257#endif
258#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
259 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
260#endif
261
262 IFX_CAT1_CLOCK_BLOCK_IMO,
263 IFX_CAT1_CLOCK_BLOCK_ECO,
264 IFX_CAT1_CLOCK_BLOCK_EXT,
265 IFX_CAT1_CLOCK_BLOCK_ILO,
266 IFX_CAT1_CLOCK_BLOCK_WCO,
267
268 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
269
270 IFX_CAT1_CLOCK_BLOCK_FLL,
271 IFX_CAT1_CLOCK_BLOCK_PLL200,
272 IFX_CAT1_CLOCK_BLOCK_PLL400,
273
274 IFX_CAT1_CLOCK_BLOCK_LF,
275 IFX_CAT1_CLOCK_BLOCK_HF,
276 IFX_CAT1_CLOCK_BLOCK_BAK,
277 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
278
279 IFX_CAT1_CLOCK_BLOCK_PERI,
280 IFX_CAT1_CLOCK_BLOCK_FAST,
281 IFX_CAT1_CLOCK_BLOCK_SLOW,
282 IFX_CAT1_CLOCK_BLOCK_MEM,
283 IFX_CAT1_CLOCK_BLOCK_TIMER,
284#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
285
286 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
287 CY_SYSCLK_DIV_8_BIT,
288 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
289 CY_SYSCLK_DIV_16_BIT,
290 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
291 CY_SYSCLK_DIV_16_5_BIT,
293 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
294 CY_SYSCLK_DIV_24_5_BIT,
296
297#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1)
298 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0),
299#endif
300#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2)
301 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1),
302#endif
303#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3)
304 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2),
305#endif
306#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4)
307 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3),
308#endif
309#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5)
310 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4),
311#endif
312#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6)
313 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5),
314#endif
315#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7)
316 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6),
317#endif
318#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8)
319 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7),
320#endif
321#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9)
322 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8),
323#endif
324#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10)
325 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9),
326#endif
327#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11)
328#warning "Unhandled PERI0 PCLK number"
329#endif
330
331#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1)
332 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0),
333#endif
334#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2)
335 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1),
336#endif
337#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3)
338 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2),
339#endif
340#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4)
341 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3),
342#endif
343#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5)
344 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4),
345#endif
346#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6)
347 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5),
348#endif
349#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7)
350#warning "Unhandled PERI1 PCLK number"
351#endif
352
353 IFX_CAT1_CLOCK_BLOCK_IHO,
354 IFX_CAT1_CLOCK_BLOCK_ECO,
355 IFX_CAT1_CLOCK_BLOCK_EXT,
356 IFX_CAT1_CLOCK_BLOCK_PILO,
357 IFX_CAT1_CLOCK_BLOCK_WCO,
358
359 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
360
361 IFX_CAT1_CLOCK_BLOCK_DPLL250,
362 IFX_CAT1_CLOCK_BLOCK_DPLL500,
363 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
364
365 IFX_CAT1_CLOCK_BLOCK_LF,
366 IFX_CAT1_CLOCK_BLOCK_MF,
367 IFX_CAT1_CLOCK_BLOCK_HF,
368
369 IFX_CAT1_CLOCK_BLOCK_BAK,
370 IFX_CAT1_CLOCK_BLOCK_PERI,
371
372#endif
373};
374
381
382struct ifx_cat1_resource_inst {
383 uint8_t type; /* !< The resource block type */
384 uint8_t block_num; /* !< The resource block index */
389 uint8_t channel_num;
390};
391
392int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
393
394en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num);
395
396static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
397 const struct ifx_cat1_clock *_clock)
398{
399#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
400 return Cy_SysClk_PeriPclkEnableDivider(
401 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
402 _clock->channel);
403#else
404 CY_UNUSED_PARAMETER(clk_dest);
405 return Cy_SysClk_PeriphEnableDivider(
406 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
407#endif
408}
409
410static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
411 const struct ifx_cat1_clock *_clock,
412 uint32_t div)
413{
414#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
415 return Cy_SysClk_PeriPclkSetDivider(
416 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
417 _clock->channel, div);
418#else
419 CY_UNUSED_PARAMETER(clk_dest);
420 return Cy_SysClk_PeriphSetDivider(IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
421 _clock->channel, div);
422#endif
423}
424
425static inline cy_rslt_t
426ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
427 const struct ifx_cat1_clock *_clock, uint32_t div_int,
428 uint32_t div_frac)
429{
430#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
431 return Cy_SysClk_PeriPclkSetFracDivider(
432 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
433 _clock->channel, div_int, div_frac);
434#else
435 CY_UNUSED_PARAMETER(clk_dest);
436 return Cy_SysClk_PeriphSetFracDivider(
437 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int,
438 div_frac);
439#endif
440}
441
442static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
443 const struct ifx_cat1_clock *_clock)
444{
445#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
446 return Cy_SysClk_PeriPclkAssignDivider(
447 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
448 _clock->channel);
449#else
450 return Cy_SysClk_PeriphAssignDivider(
451 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
452 _clock->channel);
453#endif
454}
ifx_cat1_clock_control_get_frequency
int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency)
IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE
#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block)
Definition clock_control_ifx_cat1.h:11
IFX_CAT1_CLOCK_BLOCK_PERI_GROUP
#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr)
24.5bit Peripheral Divider Group
Definition clock_control_ifx_cat1.h:17
ifx_cat1_scb_get_clock_index
en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
ifx_cat1_utils_peri_pclk_assign_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Definition clock_control_ifx_cat1.h:442
ifx_cat1_utils_peri_pclk_set_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div)
Definition clock_control_ifx_cat1.h:410
ifx_cat1_clock_block
ifx_cat1_clock_block
Definition clock_control_ifx_cat1.h:62
ifx_cat1_utils_peri_pclk_enable_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Definition clock_control_ifx_cat1.h:396
ifx_cat1_utils_peri_pclk_set_frac_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div_int, uint32_t div_frac)
Definition clock_control_ifx_cat1.h:426
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
ifx_cat1_clock
Definition clock_control_ifx_cat1.h:375
ifx_cat1_clock::funcs
const void * funcs
Definition clock_control_ifx_cat1.h:379
ifx_cat1_clock::channel
uint8_t channel
Definition clock_control_ifx_cat1.h:377
ifx_cat1_clock::block
enum ifx_cat1_clock_block block
Definition clock_control_ifx_cat1.h:376
ifx_cat1_clock::reserved
bool reserved
Definition clock_control_ifx_cat1.h:378
ifx_cat1_resource_inst
Definition clock_control_ifx_cat1.h:382
ifx_cat1_resource_inst::block_num
uint8_t block_num
Definition clock_control_ifx_cat1.h:384
ifx_cat1_resource_inst::type
uint8_t type
Definition clock_control_ifx_cat1.h:383
ifx_cat1_resource_inst::channel_num
uint8_t channel_num
The channel number, if the resource type defines multiple channels per block instance.
Definition clock_control_ifx_cat1.h:389