Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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clock_control_ifx_cat1.h
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1/*
2 * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
13
14#include <cy_sysclk.h>
15#include <cy_systick.h>
16
22
24
25#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
26
27#if !defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
28/* Converts the group/div pair into a unique block number. */
29#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
30
31#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
32 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
33 (gr), CY_SYSCLK_DIV_8_BIT), \
34 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
35 (gr), CY_SYSCLK_DIV_16_BIT), \
36 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
37 (gr), CY_SYSCLK_DIV_16_5_BIT), \
38 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
39 (gr), CY_SYSCLK_DIV_24_5_BIT)
40#else
41/* Converts the group/div pair into a unique block number. */
42#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(instance, group, div) \
43 (((group + (instance * PERI0_PERI_PCLK_PCLK_GROUP_NR)) << 2) | (div))
44#define IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCLK_PCLK_GROUP_NR)
45#define IFX_CAT1_PERIPHERAL_CLOCK_GET_GROUP(clock) \
46 ((clock >> 2) - \
47 (IFX_CAT1_PERIPHERAL_CLOCK_GET_INSTANCE(clock) * PERI0_PERI_PCLK_PCLK_GROUP_NR))
48
49#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(instance, gr) \
50 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_8BIT = \
51 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), \
52 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16BIT = \
53 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_BIT), \
54 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_16_5BIT = \
55 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_16_5_BIT), \
56 IFX_CAT1_CLOCK_BLOCK##instance##_PERIPHERAL##gr##_24_5BIT = \
57 IFX_CAT1_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_24_5_BIT)
58#endif
59
61
64#define CLK_HF0 (0U)
65#define CLK_HF1 (1U)
66#define CLK_HF2 (2U)
67#define CLK_HF3 (3U)
68#define CLK_HF4 (4U)
69#define CLK_HF5 (5U)
70#define CLK_HF6 (6U)
71#define CLK_HF7 (7U)
72#define CLK_HF8 (8U)
73#define CLK_HF9 (9U)
74#define CLK_HF10 (10U)
75#define CLK_HF11 (11U)
76#define CLK_HF12 (12U)
77#define CLK_HF13 (13U)
79
81enum ifx_cat1_clock_block {
82#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
83 /* The first four items are here for backwards compatibility with old clock APIs */
84 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT,
85 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
86 CY_SYSCLK_DIV_16_BIT,
87 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
88 CY_SYSCLK_DIV_16_5_BIT,
89 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
90 CY_SYSCLK_DIV_24_5_BIT,
91
92 IFX_CAT1_CLOCK_BLOCK_IMO,
93 IFX_CAT1_CLOCK_BLOCK_ECO,
94 IFX_CAT1_CLOCK_BLOCK_EXT,
95 IFX_CAT1_CLOCK_BLOCK_ALTHF,
96 IFX_CAT1_CLOCK_BLOCK_ALTLF,
97 IFX_CAT1_CLOCK_BLOCK_ILO,
98#if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
99 IFX_CAT1_CLOCK_BLOCK_PILO,
100#endif
101
102 IFX_CAT1_CLOCK_BLOCK_WCO,
103 IFX_CAT1_CLOCK_BLOCK_MFO,
104
105 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
106
107 IFX_CAT1_CLOCK_BLOCK_FLL,
108#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
109 IFX_CAT1_CLOCK_BLOCK_PLL200,
110 IFX_CAT1_CLOCK_BLOCK_PLL400,
111#else
112 IFX_CAT1_CLOCK_BLOCK_PLL,
113#endif
114
115 IFX_CAT1_CLOCK_BLOCK_LF,
116 IFX_CAT1_CLOCK_BLOCK_MF,
117 IFX_CAT1_CLOCK_BLOCK_HF,
118
119 IFX_CAT1_CLOCK_BLOCK_PUMP,
120 IFX_CAT1_CLOCK_BLOCK_BAK,
121 IFX_CAT1_CLOCK_BLOCK_TIMER,
122 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
123
124 IFX_CAT1_CLOCK_BLOCK_FAST,
125 IFX_CAT1_CLOCK_BLOCK_PERI,
126 IFX_CAT1_CLOCK_BLOCK_SLOW,
127
128#elif defined(COMPONENT_CAT1B)
129
130 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
131 CY_SYSCLK_DIV_8_BIT,
132 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
133 CY_SYSCLK_DIV_16_BIT,
134 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
135 CY_SYSCLK_DIV_16_5_BIT,
137 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
138 CY_SYSCLK_DIV_24_5_BIT,
140
141/* The first four items are here for backwards compatibility with old clock APIs */
142#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
143 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
144#endif
145#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
146 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
147#endif
148#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
149 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
150#endif
151#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
152 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
153#endif
154#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
155 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
156#endif
157#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
158 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
159#endif
160#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
161 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
162#endif
163#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
164 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
165#endif
166#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
167 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
168#endif
169#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
170 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
171#endif
172#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
173 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
174#endif
175#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
176 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
177#endif
178#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
179 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
180#endif
181#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
182 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
183#endif
184#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
185 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
186#endif
187#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
188 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
189#endif
190
191 IFX_CAT1_CLOCK_BLOCK_IHO,
192 IFX_CAT1_CLOCK_BLOCK_IMO,
193 IFX_CAT1_CLOCK_BLOCK_ECO,
194 IFX_CAT1_CLOCK_BLOCK_EXT,
195 IFX_CAT1_CLOCK_BLOCK_ALTHF,
196 IFX_CAT1_CLOCK_BLOCK_ALTLF,
197 IFX_CAT1_CLOCK_BLOCK_ILO,
198 IFX_CAT1_CLOCK_BLOCK_PILO,
199 IFX_CAT1_CLOCK_BLOCK_WCO,
200 IFX_CAT1_CLOCK_BLOCK_MFO,
201
202 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
203
204 IFX_CAT1_CLOCK_BLOCK_FLL,
205 IFX_CAT1_CLOCK_BLOCK_PLL200,
206 IFX_CAT1_CLOCK_BLOCK_PLL400,
207 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
208
209 IFX_CAT1_CLOCK_BLOCK_LF,
210 IFX_CAT1_CLOCK_BLOCK_MF,
211 IFX_CAT1_CLOCK_BLOCK_HF,
212
213 IFX_CAT1_CLOCK_BLOCK_PUMP,
214 IFX_CAT1_CLOCK_BLOCK_BAK,
215 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
216 IFX_CAT1_CLOCK_BLOCK_PERI,
217
218#elif defined(COMPONENT_CAT1C)
219
220 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
221 CY_SYSCLK_DIV_8_BIT,
222 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
223 CY_SYSCLK_DIV_16_BIT,
224 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
225 CY_SYSCLK_DIV_16_5_BIT,
227 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
228 CY_SYSCLK_DIV_24_5_BIT,
230
231/* The first four items are here for backwards compatibility with old clock APIs */
232#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
233 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
234#endif
235#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
236 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
237#endif
238#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
239 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
240#endif
241#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
242 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
243#endif
244#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
245 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
246#endif
247#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
248 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
249#endif
250#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
251 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
252#endif
253#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
254 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
255#endif
256#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
257 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
258#endif
259#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
260 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
261#endif
262#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
263 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
264#endif
265#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
266 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
267#endif
268#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
269 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
270#endif
271#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
272 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
273#endif
274#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
275 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
276#endif
277#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
278 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
279#endif
280
281 IFX_CAT1_CLOCK_BLOCK_IMO,
282 IFX_CAT1_CLOCK_BLOCK_ECO,
283 IFX_CAT1_CLOCK_BLOCK_EXT,
284 IFX_CAT1_CLOCK_BLOCK_ILO,
285 IFX_CAT1_CLOCK_BLOCK_WCO,
286
287 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
288
289 IFX_CAT1_CLOCK_BLOCK_FLL,
290 IFX_CAT1_CLOCK_BLOCK_PLL200,
291 IFX_CAT1_CLOCK_BLOCK_PLL400,
292
293 IFX_CAT1_CLOCK_BLOCK_LF,
294 IFX_CAT1_CLOCK_BLOCK_HF,
295 IFX_CAT1_CLOCK_BLOCK_BAK,
296 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
297
298 IFX_CAT1_CLOCK_BLOCK_PERI,
299 IFX_CAT1_CLOCK_BLOCK_FAST,
300 IFX_CAT1_CLOCK_BLOCK_SLOW,
301 IFX_CAT1_CLOCK_BLOCK_MEM,
302 IFX_CAT1_CLOCK_BLOCK_TIMER,
303#elif defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
304
305 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
306 CY_SYSCLK_DIV_8_BIT,
307 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
308 CY_SYSCLK_DIV_16_BIT,
309 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
310 CY_SYSCLK_DIV_16_5_BIT,
312 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
313 CY_SYSCLK_DIV_24_5_BIT,
315
316#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 1)
317 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 0),
318#endif
319#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 2)
320 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 1),
321#endif
322#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 3)
323 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 2),
324#endif
325#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 4)
326 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 3),
327#endif
328#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 5)
329 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 4),
330#endif
331#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 6)
332 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 5),
333#endif
334#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 7)
335 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 6),
336#endif
337#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 8)
338 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 7),
339#endif
340#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 9)
341 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 8),
342#endif
343#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 10)
344 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0, 9),
345#endif
346#if (PERI0_PERI_PCLK_PCLK_GROUP_NR >= 11)
347#warning "Unhandled PERI0 PCLK number"
348#endif
349
350#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 1)
351 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 0),
352#endif
353#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 2)
354 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 1),
355#endif
356#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 3)
357 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 2),
358#endif
359#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 4)
360 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 3),
361#endif
362#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 5)
363 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 4),
364#endif
365#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 6)
366 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1, 5),
367#endif
368#if (PERI1_PERI_PCLK_PCLK_GROUP_NR >= 7)
369#warning "Unhandled PERI1 PCLK number"
370#endif
371
372 IFX_CAT1_CLOCK_BLOCK_IHO,
373 IFX_CAT1_CLOCK_BLOCK_ECO,
374 IFX_CAT1_CLOCK_BLOCK_EXT,
375 IFX_CAT1_CLOCK_BLOCK_PILO,
376 IFX_CAT1_CLOCK_BLOCK_WCO,
377
378 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
379
380 IFX_CAT1_CLOCK_BLOCK_DPLL250,
381 IFX_CAT1_CLOCK_BLOCK_DPLL500,
382 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
383
384 IFX_CAT1_CLOCK_BLOCK_LF,
385 IFX_CAT1_CLOCK_BLOCK_MF,
386 IFX_CAT1_CLOCK_BLOCK_HF,
387
388 IFX_CAT1_CLOCK_BLOCK_BAK,
389 IFX_CAT1_CLOCK_BLOCK_PERI,
390
391#elif defined(CONFIG_SOC_FAMILY_INFINEON_PSOC4)
392 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
393 CY_SYSCLK_DIV_16_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_BIT */
394
395 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
396 CY_SYSCLK_DIV_16_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */
397
398 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
399 CY_SYSCLK_DIV_24_5_BIT, /* Equal to IFX_CAT1_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */
400#endif
401};
402
412
423
433int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
434
442static inline uint32_t ifx_cat1_utils_peri_pclk_get_frequency(en_clk_dst_t clk_dest,
443 const struct ifx_cat1_clock *_clock)
444{
445#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
446 return Cy_SysClk_PeriPclkGetFrequency(
447 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
448 _clock->channel);
449#else
450 CY_UNUSED_PARAMETER(clk_dest);
451 return Cy_SysClk_PeriphGetFrequency(
452 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
453#endif
454}
455
463static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
464 const struct ifx_cat1_clock *_clock)
465{
466#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
467 return Cy_SysClk_PeriPclkEnableDivider(
468 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
469 _clock->channel);
470#else
471 CY_UNUSED_PARAMETER(clk_dest);
472 return Cy_SysClk_PeriphEnableDivider(
473 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
474#endif
475}
476
485static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
486 const struct ifx_cat1_clock *_clock,
487 uint32_t div)
488{
489#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
490 return Cy_SysClk_PeriPclkSetDivider(
491 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
492 _clock->channel, div);
493#else
494 CY_UNUSED_PARAMETER(clk_dest);
495 return Cy_SysClk_PeriphSetDivider(IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
496 _clock->channel, div);
497#endif
498}
499
509static inline cy_rslt_t
510ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
511 const struct ifx_cat1_clock *_clock, uint32_t div_int,
512 uint32_t div_frac)
513{
514#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
515 return Cy_SysClk_PeriPclkSetFracDivider(
516 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
517 _clock->channel, div_int, div_frac);
518#else
519 CY_UNUSED_PARAMETER(clk_dest);
520 return Cy_SysClk_PeriphSetFracDivider(
521 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int,
522 div_frac);
523#endif
524}
525
533static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
534 const struct ifx_cat1_clock *_clock)
535{
536#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
537 return Cy_SysClk_PeriPclkAssignDivider(
538 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
539 _clock->channel);
540#else
541 return Cy_SysClk_PeriphAssignDivider(
542 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
543 _clock->channel);
544#endif
545}
546
547#if defined(CONFIG_SOC_FAMILY_INFINEON_EDGE)
555#define IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(instance, group) (((instance) << 4) | (group))
556
566static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
567{
568 switch (peri_group) {
569 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 0):
570 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 4):
571 return CLK_HF0;
572 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 7):
573 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 0):
574 return CLK_HF1;
575 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 3):
576 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 2):
577 return CLK_HF5;
578 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 4):
579 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 3):
580 return CLK_HF6;
581 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(1, 1):
582 return CLK_HF7;
583 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 2):
584 return CLK_HF9;
585 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 1):
586 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 5):
587 return CLK_HF10;
588 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 8):
589 return CLK_HF11;
590 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 6):
591 case IFX_CAT1_PERIPHERAL_INSTANCE_GROUP(0, 9):
592 return CLK_HF13;
593 default:
594 break;
595 }
596 return -EINVAL;
597}
598
599#elif defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
609static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
610{
611 switch (peri_group) {
612 case 0:
613 case 2:
614 return CLK_HF0;
615 case 1:
616 case 3:
617 return CLK_HF1;
618 case 4:
619 return CLK_HF2;
620 case 5:
621 return CLK_HF3;
622 case 6:
623 return CLK_HF4;
624 default:
625 break;
626 }
627 return -EINVAL;
628}
629
630#else /* !CONFIG_SOC_FAMILY_INFINEON_EDGE && !CONFIG_SOC_FAMILY_INFINEON_CAT1B */
640static inline uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
641{
642 ARG_UNUSED(peri_group);
643
644 return -EINVAL;
645}
646#endif
647
ifx_cat1_clock_control_get_frequency
int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency)
Get the frequency of a clock identified by its Devicetree ordinal.
CLK_HF4
#define CLK_HF4
HF clock 4.
Definition clock_control_ifx_cat1.h:68
ifx_cat1_utils_peri_pclk_get_frequency
static uint32_t ifx_cat1_utils_peri_pclk_get_frequency(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Get the frequency of a peripheral clock divider.
Definition clock_control_ifx_cat1.h:442
CLK_HF9
#define CLK_HF9
HF clock 9.
Definition clock_control_ifx_cat1.h:73
CLK_HF13
#define CLK_HF13
HF clock 13.
Definition clock_control_ifx_cat1.h:77
CLK_HF5
#define CLK_HF5
HF clock 5.
Definition clock_control_ifx_cat1.h:69
CLK_HF3
#define CLK_HF3
HF clock 3.
Definition clock_control_ifx_cat1.h:67
ifx_cat1_utils_peri_pclk_assign_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Assign a divider to a peripheral clock destination.
Definition clock_control_ifx_cat1.h:533
CLK_HF10
#define CLK_HF10
HF clock 10.
Definition clock_control_ifx_cat1.h:74
CLK_HF0
#define CLK_HF0
HF clock 0.
Definition clock_control_ifx_cat1.h:64
ifx_cat1_utils_peri_pclk_set_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div)
Set the integer divider for a peripheral clock.
Definition clock_control_ifx_cat1.h:485
CLK_HF2
#define CLK_HF2
HF clock 2.
Definition clock_control_ifx_cat1.h:66
ifx_cat1_clock_block
ifx_cat1_clock_block
CAT1 clock block (source or domain) selector.
Definition clock_control_ifx_cat1.h:81
ifx_cat1_utils_peri_pclk_enable_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Enable the divider associated with a peripheral clock.
Definition clock_control_ifx_cat1.h:463
CLK_HF1
#define CLK_HF1
HF clock 1.
Definition clock_control_ifx_cat1.h:65
ifx_cat1_utils_peri_pclk_set_frac_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div_int, uint32_t div_frac)
Set the fractional divider for a peripheral clock.
Definition clock_control_ifx_cat1.h:510
CLK_HF6
#define CLK_HF6
HF clock 6.
Definition clock_control_ifx_cat1.h:70
CLK_HF7
#define CLK_HF7
HF clock 7.
Definition clock_control_ifx_cat1.h:71
CLK_HF11
#define CLK_HF11
HF clock 11.
Definition clock_control_ifx_cat1.h:75
ifx_cat1_utils_peri_pclk_get_hfclk
static uint8_t ifx_cat1_utils_peri_pclk_get_hfclk(uint8_t peri_group)
Map a peripheral group index to the HF clock that sources it.
Definition clock_control_ifx_cat1.h:640
EINVAL
#define EINVAL
Invalid argument.
Definition errno.h:60
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
ifx_cat1_clock
CAT1 clock descriptor.
Definition clock_control_ifx_cat1.h:404
ifx_cat1_clock::group
uint8_t group
Peripheral clock group number.
Definition clock_control_ifx_cat1.h:408
ifx_cat1_clock::instance
uint8_t instance
Peripheral clock instance number.
Definition clock_control_ifx_cat1.h:407
ifx_cat1_clock::funcs
const void * funcs
Clock-specific functions.
Definition clock_control_ifx_cat1.h:410
ifx_cat1_clock::channel
uint8_t channel
Clock channel number.
Definition clock_control_ifx_cat1.h:406
ifx_cat1_clock::block
enum ifx_cat1_clock_block block
Clock block type.
Definition clock_control_ifx_cat1.h:405
ifx_cat1_clock::reserved
bool reserved
Reserved for future use.
Definition clock_control_ifx_cat1.h:409
ifx_cat1_resource_inst
CAT1 resource instance descriptor.
Definition clock_control_ifx_cat1.h:414
ifx_cat1_resource_inst::block_num
uint8_t block_num
The resource block index.
Definition clock_control_ifx_cat1.h:416
ifx_cat1_resource_inst::type
uint8_t type
The resource block type.
Definition clock_control_ifx_cat1.h:415
ifx_cat1_resource_inst::channel_num
uint8_t channel_num
The channel number, if the resource type defines multiple channels per block instance.
Definition clock_control_ifx_cat1.h:421