15#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NUMAKER_H_
16#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NUMAKER_H_
26#define NUMAKER_SCC_CLKSW_UNTOUCHED 0
27#define NUMAKER_SCC_CLKSW_ENABLE 1
28#define NUMAKER_SCC_CLKSW_DISABLE 2
32#define NUMAKER_SCC_SUBSYS_ID_PCC 1
46#if defined(CONFIG_SOC_SERIES_M55M1X)
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
Peripheral clock control rate information.
Definition clock_control_numaker.h:45
uint32_t clk_src_rate
Clock source rate, in Hz.
Definition clock_control_numaker.h:52
uint32_t clk_div_value
Decoded clock divider value.
Definition clock_control_numaker.h:53
uint32_t clk_modidx_real
Resolved module index.
Definition clock_control_numaker.h:49
uint32_t clk_src_idx
Decoded clock source index of clk_src.
Definition clock_control_numaker.h:51
uint32_t clk_div_value_max
Maximum supported divider value.
Definition clock_control_numaker.h:54
uint32_t clk_mod_rate
Resulting module clock rate, in Hz.
Definition clock_control_numaker.h:55
Peripheral clock control configuration.
Definition clock_control_numaker.h:35
uint32_t clk_modidx
Module index (u32ModuleIdx/u64ModuleIdx in BSP CLK_SetModuleClock()).
Definition clock_control_numaker.h:37
uint32_t clk_src
Clock source (u32ClkSrc in BSP CLK_SetModuleClock()).
Definition clock_control_numaker.h:39
uint32_t clk_div
Clock divider (u32ClkDiv in BSP CLK_SetModuleClock()).
Definition clock_control_numaker.h:41
NuMaker clock subsystem rate selector.
Definition clock_control_numaker.h:68
struct numaker_scc_subsys_pcc_rate pcc
Peripheral clock rate information.
Definition clock_control_numaker.h:70
NuMaker clock subsystem selector.
Definition clock_control_numaker.h:59
uint32_t subsys_id
SCC subsystem ID (see NUMAKER_SCC_SUBSYS_ID_PCC).
Definition clock_control_numaker.h:60
struct numaker_scc_subsys_pcc pcc
Peripheral clock configuration.
Definition clock_control_numaker.h:63