Zephyr API Documentation 4.3.99
A Scalable Open Source RTOS
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common-clock.h
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1
6
7 /*
8 * Copyright (c) 2024 Silicon Laboratories Inc.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 */
12
13#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
14#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
15
27
29
30/*
31 * DT macros for clock branches.
32 * Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be
33 * interpreted correctly by the clock control driver.
34 */
35#define CLOCK_BRANCH_SYSCLK 0
36#define CLOCK_BRANCH_HCLK 1
37#define CLOCK_BRANCH_HCLKRADIO 2
38#define CLOCK_BRANCH_PCLK 3
39#define CLOCK_BRANCH_LSPCLK 4
40#define CLOCK_BRANCH_TRACECLK 5
41#define CLOCK_BRANCH_ADCCLK 6
42#define CLOCK_BRANCH_EXPORTCLK 7
43#define CLOCK_BRANCH_EM01GRPACLK 8
44#define CLOCK_BRANCH_EM01GRPBCLK 9
45#define CLOCK_BRANCH_EM01GRPCCLK 10
46#define CLOCK_BRANCH_EM01GRPDCLK 11
47#define CLOCK_BRANCH_EM23GRPACLK 12
48#define CLOCK_BRANCH_EM4GRPACLK 13
49#define CLOCK_BRANCH_QSPISYSCLK 14
50#define CLOCK_BRANCH_IADCCLK 15
51#define CLOCK_BRANCH_WDOG0CLK 16
52#define CLOCK_BRANCH_WDOG1CLK 17
53#define CLOCK_BRANCH_RTCCCLK 18
54#define CLOCK_BRANCH_SYSRTCCLK 19
55#define CLOCK_BRANCH_EUART0CLK 20
56#define CLOCK_BRANCH_EUSART0CLK 21
57#define CLOCK_BRANCH_EUSART1CLK 22
58#define CLOCK_BRANCH_DPLLREFCLK 23
59#define CLOCK_BRANCH_I2C0CLK 24
60#define CLOCK_BRANCH_LCDCLK 25
61#define CLOCK_BRANCH_PIXELRZCLK 26
62#define CLOCK_BRANCH_PCNT0CLK 27
63#define CLOCK_BRANCH_PRORTCCLK 28
64#define CLOCK_BRANCH_SYSTICKCLK 29
65#define CLOCK_BRANCH_LESENSEHFCLK 30
66#define CLOCK_BRANCH_VDAC0CLK 31
67#define CLOCK_BRANCH_VDAC1CLK 32
68#define CLOCK_BRANCH_USB0CLK 33
69#define CLOCK_BRANCH_FLPLLREFCLK 34
70#define CLOCK_BRANCH_PDM0CLK 35
71#define CLOCK_BRANCH_INVALID 36
72
73#define CLOCK_BIT_MASK 0x03FUL
74#define CLOCK_REG_MASK 0x1C0UL
75
77
81
82#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */