7#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_TIMER_H_
8#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_TIMER_H_
10#ifdef CONFIG_ARM_ARCH_TIMER
22#define ARM_ARCH_TIMER_BASE DT_REG_ADDR_BY_IDX(ARM_TIMER_NODE, 0)
23#define ARM_ARCH_TIMER_IRQ ARM_TIMER_VIRTUAL_IRQ
24#define ARM_ARCH_TIMER_PRIO ARM_TIMER_VIRTUAL_PRIO
25#define ARM_ARCH_TIMER_FLAGS ARM_TIMER_VIRTUAL_FLAGS
27#define TIMER_CNT_LOWER 0x00
28#define TIMER_CNT_UPPER 0x04
29#define TIMER_CTRL 0x08
31#define TIMER_CMP_LOWER 0x10
32#define TIMER_CMP_UPPER 0x14
34#define TIMER_IRQ_ENABLE BIT(2)
35#define TIMER_COMP_ENABLE BIT(1)
36#define TIMER_ENABLE BIT(0)
38#define TIMER_ISR_EVENT_FLAG BIT(0)
42#define TIMER_REG_GET(offs) (DEVICE_MMIO_TOPLEVEL_GET(timer_regs) + offs)
57 ctrl &= ~(TIMER_COMP_ENABLE | TIMER_IRQ_ENABLE);
64 ctrl |= TIMER_COMP_ENABLE;
68#if defined(CONFIG_ARM_ARCH_TIMER_ERRATUM_740657)
85static ALWAYS_INLINE void arm_arch_timer_clear_int_status(
void)
87 sys_write32(TIMER_ISR_EVENT_FLAG, TIMER_REG_GET(TIMER_ISR));
100 ctrl &= ~TIMER_ENABLE;
112 ctrl &= ~TIMER_IRQ_ENABLE;
114 ctrl |= TIMER_IRQ_ENABLE;
134 upper =
sys_read32(TIMER_REG_GET(TIMER_CNT_UPPER));
137 lower =
sys_read32(TIMER_REG_GET(TIMER_CNT_LOWER));
138 upper =
sys_read32(TIMER_REG_GET(TIMER_CNT_UPPER));
139 }
while (upper != upper_saved);
141 return ((
uint64_t)upper) << 32 | lower;
#define ARM_TIMER_NODE
Definition arm_arch_timer.h:14
static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
Definition armv8_timer.h:63
static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
Definition armv8_timer.h:48
static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
Definition armv8_timer.h:28
static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
Definition armv8_timer.h:33
static ALWAYS_INLINE void arm_arch_timer_init(void)
Definition armv8_timer.h:24
#define DEVICE_MMIO_TOPLEVEL_MAP(name, flags)
Set up memory for a driver'sMMIO region.
Definition device_mmio.h:715
#define DEVICE_MMIO_TOPLEVEL_STATIC(name, node_id)
Declare top-level storage for MMIO information, static scope.
Definition device_mmio.h:661
#define K_MEM_CACHE_NONE
No caching.
Definition mm.h:34
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
Definition sys-io-common.h:70
static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
Definition sys-io-common.h:59