Zephyr API Documentation
4.0.99
A Scalable Open Source RTOS
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esai.h
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
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#define _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
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/* ESAI pin IDs
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* the values of these macros are meant to match
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* the bit position from PCRC/PRRC's PC/PDC associated
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* with each of these pins.
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*/
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#define ESAI_PIN_SCKR 0
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#define ESAI_PIN_FSR 1
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#define ESAI_PIN_HCKR 2
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#define ESAI_PIN_SCKT 3
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#define ESAI_PIN_FST 4
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#define ESAI_PIN_HCKT 5
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#define ESAI_PIN_SDO5_SDI0 6
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#define ESAI_PIN_SDO4_SDI1 7
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#define ESAI_PIN_SDO3_SDI2 8
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#define ESAI_PIN_SDO2_SDI3 9
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#define ESAI_PIN_SDO1 10
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#define ESAI_PIN_SDO0 11
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/* ESAI pin modes
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* the values of these macros are set according to
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* the following table:
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*
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* PDC = 0, PC = 0 => DISCONNECTED (0)
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* PDC = 0, PC = 1 => GPIO INPUT (1)
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* PDC = 1, PC = 0 => GPIO OUTPUT (2)
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* PDC = 1, PC = 1 => ESAI (3)
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*/
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#define ESAI_PIN_DISCONNECTED 0
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#define ESAI_PIN_GPIO_INPUT 1
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#define ESAI_PIN_GPIO_OUTPUT 2
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#define ESAI_PIN_ESAI 3
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/* ESAI clock IDs */
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#define ESAI_CLOCK_HCKT 0
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#define ESAI_CLOCK_HCKR 1
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#define ESAI_CLOCK_SCKR 2
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#define ESAI_CLOCK_SCKT 3
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#define ESAI_CLOCK_FSR 4
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#define ESAI_CLOCK_FST 5
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/* ESAI clock directions */
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#define ESAI_CLOCK_INPUT 0
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#define ESAI_CLOCK_OUTPUT 1
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#endif
/* _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ */
zephyr
dt-bindings
dai
esai.h
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