Zephyr API Documentation 4.0.0-rc3
A Scalable Open Source RTOS
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esai.h
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1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
8#define _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
9
10/* ESAI pin IDs
11 * the values of these macros are meant to match
12 * the bit position from PCRC/PRRC's PC/PDC associated
13 * with each of these pins.
14 */
15#define ESAI_PIN_SCKR 0
16#define ESAI_PIN_FSR 1
17#define ESAI_PIN_HCKR 2
18#define ESAI_PIN_SCKT 3
19#define ESAI_PIN_FST 4
20#define ESAI_PIN_HCKT 5
21#define ESAI_PIN_SDO5_SDI0 6
22#define ESAI_PIN_SDO4_SDI1 7
23#define ESAI_PIN_SDO3_SDI2 8
24#define ESAI_PIN_SDO2_SDI3 9
25#define ESAI_PIN_SDO1 10
26#define ESAI_PIN_SDO0 11
27
28/* ESAI pin modes
29 * the values of these macros are set according to
30 * the following table:
31 *
32 * PDC = 0, PC = 0 => DISCONNECTED (0)
33 * PDC = 0, PC = 1 => GPIO INPUT (1)
34 * PDC = 1, PC = 0 => GPIO OUTPUT (2)
35 * PDC = 1, PC = 1 => ESAI (3)
36 */
37#define ESAI_PIN_DISCONNECTED 0
38#define ESAI_PIN_GPIO_INPUT 1
39#define ESAI_PIN_GPIO_OUTPUT 2
40#define ESAI_PIN_ESAI 3
41
42/* ESAI clock IDs */
43#define ESAI_CLOCK_HCKT 0
44#define ESAI_CLOCK_HCKR 1
45#define ESAI_CLOCK_SCKR 2
46#define ESAI_CLOCK_SCKT 3
47#define ESAI_CLOCK_FSR 4
48#define ESAI_CLOCK_FST 5
49
50/* ESAI clock directions */
51#define ESAI_CLOCK_INPUT 0
52#define ESAI_CLOCK_OUTPUT 1
53
54#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ */