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4.0.99
A Scalable Open Source RTOS
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esp-esp32c3-intmux.h
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0
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#define WIFI_MAC_NMI_SOURCE 1
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#define WIFI_PWR_INTR_SOURCE 2
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#define WIFI_BB_INTR_SOURCE 3
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#define BT_MAC_INTR_SOURCE 4
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#define BT_BB_INTR_SOURCE 5
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#define BT_BB_NMI_SOURCE 6
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#define RWBT_INTR_SOURCE 7
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#define RWBLE_INTR_SOURCE 8
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#define RWBT_NMI_SOURCE 9
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#define RWBLE_NMI_SOURCE 10
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#define I2C_MASTER_SOURCE 11
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#define SLC0_INTR_SOURCE 12
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#define SLC1_INTR_SOURCE 13
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#define APB_CTRL_INTR_SOURCE 14
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#define UHCI0_INTR_SOURCE 15
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#define GPIO_INTR_SOURCE 16
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#define GPIO_NMI_SOURCE 17
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#define SPI1_INTR_SOURCE 18
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#define SPI2_INTR_SOURCE 19
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#define I2S1_INTR_SOURCE 20
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#define UART0_INTR_SOURCE 21
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#define UART1_INTR_SOURCE 22
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#define LEDC_INTR_SOURCE 23
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#define EFUSE_INTR_SOURCE 24
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#define TWAI_INTR_SOURCE 25
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#define USB_INTR_SOURCE 26
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#define RTC_CORE_INTR_SOURCE 27
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#define RMT_INTR_SOURCE 28
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#define I2C_EXT0_INTR_SOURCE 29
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#define TIMER1_INTR_SOURCE 30
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#define TIMER2_INTR_SOURCE 31
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#define TG0_T0_LEVEL_INTR_SOURCE 32
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#define TG0_WDT_LEVEL_INTR_SOURCE 33
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#define TG1_T0_LEVEL_INTR_SOURCE 34
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#define TG1_WDT_LEVEL_INTR_SOURCE 35
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#define CACHE_IA_INTR_SOURCE 36
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
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#define ICACHE_PRELOAD0_INTR_SOURCE 41
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#define ICACHE_SYNC0_INTR_SOURCE 42
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#define APB_ADC_INTR_SOURCE 43
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#define DMA_CH0_INTR_SOURCE 44
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#define DMA_CH1_INTR_SOURCE 45
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#define DMA_CH2_INTR_SOURCE 46
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#define RSA_INTR_SOURCE 47
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#define AES_INTR_SOURCE 48
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#define SHA_INTR_SOURCE 49
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#define FROM_CPU_INTR0_SOURCE 50
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#define FROM_CPU_INTR1_SOURCE 51
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#define FROM_CPU_INTR2_SOURCE 52
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#define FROM_CPU_INTR3_SOURCE 53
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#define ASSIST_DEBUG_INTR_SOURCE 54
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#define DMA_APBPERI_PMS_INTR_SOURCE 55
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#define CORE0_IRAM0_PMS_INTR_SOURCE 56
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#define CORE0_DRAM0_PMS_INTR_SOURCE 57
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#define CORE0_PIF_PMS_INTR_SOURCE 58
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
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#define BAK_PMS_VIOLATE_INTR_SOURCE 60
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#define CACHE_CORE0_ACS_INTR_SOURCE 61
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/* RISC-V supports priority values from 1 (lowest) to 15.
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* As interrupt controller for Xtensa and RISC-V is shared, this is
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* set to an intermediate and compatible value.
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*/
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#define IRQ_DEFAULT_PRIORITY 3
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#define ESP_INTR_FLAG_SHARED (1<<8)
/* Interrupt can be shared between ISRs */
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#endif
zephyr
dt-bindings
interrupt-controller
esp-esp32c3-intmux.h
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