Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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esp-esp32p4-intmux.h
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1/*
2 * Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14
15#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_
16#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_
17
36
38
39/* Derived from components/soc/esp32p4/include/soc/interrupts.h */
40#define LP_RTC_INTR_SOURCE 0
41#define LP_WDT_INTR_SOURCE 1
42#define LP_TIMER_REG0_INTR_SOURCE 2
43#define LP_TIMER_REG1_INTR_SOURCE 3
44#define MB_HP_INTR_SOURCE 4
45#define MB_LP_INTR_SOURCE 5
46#define PMU_0_INTR_SOURCE 6
47#define PMU_1_INTR_SOURCE 7
48#define LP_ANAPERI_INTR_SOURCE 8
49#define LP_ADC_INTR_SOURCE 9
50#define LP_GPIO_INTR_SOURCE 10
51#define LP_I2C_INTR_SOURCE 11
52#define LP_I2S_INTR_SOURCE 12
53#define LP_SPI_INTR_SOURCE 13
54#define LP_TOUCH_INTR_SOURCE 14
55#define LP_TSENS_INTR_SOURCE 15
56#define LP_UART_INTR_SOURCE 16
57#define LP_EFUSE_INTR_SOURCE 17
58#define LP_SW_INTR_SOURCE 18
59#define LP_SYSREG_INTR_SOURCE 19
60#define LP_HUK_INTR_SOURCE 20
61#define SYS_ICM_INTR_SOURCE 21
62#define USB_SERIAL_JTAG_INTR_SOURCE 22
63#define SDIO_HOST_INTR_SOURCE 23
64#define DW_GDMA_INTR_SOURCE 24
65#define SPI2_INTR_SOURCE 25
66#define SPI3_INTR_SOURCE 26
67#define I2S0_INTR_SOURCE 27
68#define I2S1_INTR_SOURCE 28
69#define I2S2_INTR_SOURCE 29
70#define UHCI0_INTR_SOURCE 30
71#define UART0_INTR_SOURCE 31
72#define UART1_INTR_SOURCE 32
73#define UART2_INTR_SOURCE 33
74#define UART3_INTR_SOURCE 34
75#define UART4_INTR_SOURCE 35
76#define LCD_CAM_INTR_SOURCE 36
77#define ADC_INTR_SOURCE 37
78#define PWM0_INTR_SOURCE 38
79#define PWM1_INTR_SOURCE 39
80#define TWAI0_INTR_SOURCE 40
81#define TWAI1_INTR_SOURCE 41
82#define TWAI2_INTR_SOURCE 42
83#define RMT_INTR_SOURCE 43
84#define I2C0_INTR_SOURCE 44
85#define I2C1_INTR_SOURCE 45
86#define TG0_T0_LEVEL_INTR_SOURCE 46
87#define TG0_T1_LEVEL_INTR_SOURCE 47
88#define TG0_WDT_LEVEL_INTR_SOURCE 48
89#define TG1_T0_LEVEL_INTR_SOURCE 49
90#define TG1_T1_LEVEL_INTR_SOURCE 50
91#define TG1_WDT_LEVEL_INTR_SOURCE 51
92#define LEDC_INTR_SOURCE 52
93#define SYSTIMER_TARGET0_INTR_SOURCE 53
94#define SYSTIMER_TARGET1_INTR_SOURCE 54
95#define SYSTIMER_TARGET2_INTR_SOURCE 55
96#define AHB_PDMA_IN_CH0_INTR_SOURCE 56
97#define AHB_PDMA_IN_CH1_INTR_SOURCE 57
98#define AHB_PDMA_IN_CH2_INTR_SOURCE 58
99#define AHB_PDMA_OUT_CH0_INTR_SOURCE 59
100#define AHB_PDMA_OUT_CH1_INTR_SOURCE 60
101#define AHB_PDMA_OUT_CH2_INTR_SOURCE 61
102#define AXI_PDMA_IN_CH0_INTR_SOURCE 62
103#define AXI_PDMA_IN_CH1_INTR_SOURCE 63
104#define AXI_PDMA_IN_CH2_INTR_SOURCE 64
105#define AXI_PDMA_OUT_CH0_INTR_SOURCE 65
106#define AXI_PDMA_OUT_CH1_INTR_SOURCE 66
107#define AXI_PDMA_OUT_CH2_INTR_SOURCE 67
108#define RSA_INTR_SOURCE 68
109#define AES_INTR_SOURCE 69
110#define SHA_INTR_SOURCE 70
111#define ECC_INTR_SOURCE 71
112#define ECDSA_INTR_SOURCE 72
113#define KM_INTR_SOURCE 73
114#define GPIO_INTR0_SOURCE 74
115#define GPIO_INTR1_SOURCE 75
116#define GPIO_INTR2_SOURCE 76
117#define GPIO_INTR3_SOURCE 77
118#define GPIO_PAD_COMP_INTR_SOURCE 78
119#define FROM_CPU_INTR0_SOURCE 79
120#define FROM_CPU_INTR1_SOURCE 80
121#define FROM_CPU_INTR2_SOURCE 81
122#define FROM_CPU_INTR3_SOURCE 82
123#define CACHE_INTR_SOURCE 83
124#define MSPI_INTR_SOURCE 84
125#define CSI_BRIDGE_INTR_SOURCE 85
126#define DSI_BRIDGE_INTR_SOURCE 86
127#define CSI_INTR_SOURCE 87
128#define DSI_INTR_SOURCE 88
129#define GMII_PHY_INTR_SOURCE 89
130#define LPI_INTR_SOURCE 90
131#define PMT_INTR_SOURCE 91
132#define ETH_MAC_INTR_SOURCE 92
133#define USB_OTG_INTR_SOURCE 93
134#define USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE 94
135#define JPEG_INTR_SOURCE 95
136#define PPA_INTR_SOURCE 96
137#define CORE0_TRACE_INTR_SOURCE 97
138#define CORE1_TRACE_INTR_SOURCE 98
139#define HP_CORE_CTRL_INTR_SOURCE 99
140#define ISP_INTR_SOURCE 100
141#define I3C_MST_INTR_SOURCE 101
142#define I3C_SLV_INTR_SOURCE 102
143#define USB_OTG11_CH0_INTR_SOURCE 103
144#define DMA2D_IN_CH0_INTR_SOURCE 104
145#define DMA2D_IN_CH1_INTR_SOURCE 105
146#define DMA2D_OUT_CH0_INTR_SOURCE 106
147#define DMA2D_OUT_CH1_INTR_SOURCE 107
148#define DMA2D_OUT_CH2_INTR_SOURCE 108
149#define PSRAM_MSPI_INTR_SOURCE 109
150#define HP_SYSREG_INTR_SOURCE 110
151#define PCNT_INTR_SOURCE 111
152#define HP_PAU_INTR_SOURCE 112
153#define HP_PARLIO_RX_INTR_SOURCE 113
154#define HP_PARLIO_TX_INTR_SOURCE 114
155#define ASSIST_DEBUG_INTR_SOURCE 120
156
162#define IRQ_DEFAULT_PRIORITY 0
163
165
167
168#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_ */