Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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esp-esp32p4-intmux.h
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1/*
2 * Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
13
14#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_
15#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_
16
17/* Derived from components/soc/esp32p4/include/soc/interrupts.h */
18#define LP_RTC_INTR_SOURCE 0
19#define LP_WDT_INTR_SOURCE 1
20#define LP_TIMER_REG0_INTR_SOURCE 2
21#define LP_TIMER_REG1_INTR_SOURCE 3
22#define MB_HP_INTR_SOURCE 4
23#define MB_LP_INTR_SOURCE 5
24#define PMU_0_INTR_SOURCE 6
25#define PMU_1_INTR_SOURCE 7
26#define LP_ANAPERI_INTR_SOURCE 8
27#define LP_ADC_INTR_SOURCE 9
28#define LP_GPIO_INTR_SOURCE 10
29#define LP_I2C_INTR_SOURCE 11
30#define LP_I2S_INTR_SOURCE 12
31#define LP_SPI_INTR_SOURCE 13
32#define LP_TOUCH_INTR_SOURCE 14
33#define LP_TSENS_INTR_SOURCE 15
34#define LP_UART_INTR_SOURCE 16
35#define LP_EFUSE_INTR_SOURCE 17
36#define LP_SW_INTR_SOURCE 18
37#define LP_SYSREG_INTR_SOURCE 19
38#define LP_HUK_INTR_SOURCE 20
39#define SYS_ICM_INTR_SOURCE 21
40#define USB_SERIAL_JTAG_INTR_SOURCE 22
41#define SDIO_HOST_INTR_SOURCE 23
42#define DW_GDMA_INTR_SOURCE 24
43#define SPI2_INTR_SOURCE 25
44#define SPI3_INTR_SOURCE 26
45#define I2S0_INTR_SOURCE 27
46#define I2S1_INTR_SOURCE 28
47#define I2S2_INTR_SOURCE 29
48#define UHCI0_INTR_SOURCE 30
49#define UART0_INTR_SOURCE 31
50#define UART1_INTR_SOURCE 32
51#define UART2_INTR_SOURCE 33
52#define UART3_INTR_SOURCE 34
53#define UART4_INTR_SOURCE 35
54#define LCD_CAM_INTR_SOURCE 36
55#define ADC_INTR_SOURCE 37
56#define PWM0_INTR_SOURCE 38
57#define PWM1_INTR_SOURCE 39
58#define TWAI0_INTR_SOURCE 40
59#define TWAI1_INTR_SOURCE 41
60#define TWAI2_INTR_SOURCE 42
61#define RMT_INTR_SOURCE 43
62#define I2C0_INTR_SOURCE 44
63#define I2C1_INTR_SOURCE 45
64#define TG0_T0_LEVEL_INTR_SOURCE 46
65#define TG0_T1_LEVEL_INTR_SOURCE 47
66#define TG0_WDT_LEVEL_INTR_SOURCE 48
67#define TG1_T0_LEVEL_INTR_SOURCE 49
68#define TG1_T1_LEVEL_INTR_SOURCE 50
69#define TG1_WDT_LEVEL_INTR_SOURCE 51
70#define LEDC_INTR_SOURCE 52
71#define SYSTIMER_TARGET0_INTR_SOURCE 53
72#define SYSTIMER_TARGET1_INTR_SOURCE 54
73#define SYSTIMER_TARGET2_INTR_SOURCE 55
74#define AHB_PDMA_IN_CH0_INTR_SOURCE 56
75#define AHB_PDMA_IN_CH1_INTR_SOURCE 57
76#define AHB_PDMA_IN_CH2_INTR_SOURCE 58
77#define AHB_PDMA_OUT_CH0_INTR_SOURCE 59
78#define AHB_PDMA_OUT_CH1_INTR_SOURCE 60
79#define AHB_PDMA_OUT_CH2_INTR_SOURCE 61
80#define AXI_PDMA_IN_CH0_INTR_SOURCE 62
81#define AXI_PDMA_IN_CH1_INTR_SOURCE 63
82#define AXI_PDMA_IN_CH2_INTR_SOURCE 64
83#define AXI_PDMA_OUT_CH0_INTR_SOURCE 65
84#define AXI_PDMA_OUT_CH1_INTR_SOURCE 66
85#define AXI_PDMA_OUT_CH2_INTR_SOURCE 67
86#define RSA_INTR_SOURCE 68
87#define AES_INTR_SOURCE 69
88#define SHA_INTR_SOURCE 70
89#define ECC_INTR_SOURCE 71
90#define ECDSA_INTR_SOURCE 72
91#define KM_INTR_SOURCE 73
92#define GPIO_INTR0_SOURCE 74
93#define GPIO_INTR1_SOURCE 75
94#define GPIO_INTR2_SOURCE 76
95#define GPIO_INTR3_SOURCE 77
96#define GPIO_PAD_COMP_INTR_SOURCE 78
97#define FROM_CPU_INTR0_SOURCE 79
98#define FROM_CPU_INTR1_SOURCE 80
99#define FROM_CPU_INTR2_SOURCE 81
100#define FROM_CPU_INTR3_SOURCE 82
101#define CACHE_INTR_SOURCE 83
102#define MSPI_INTR_SOURCE 84
103#define CSI_BRIDGE_INTR_SOURCE 85
104#define DSI_BRIDGE_INTR_SOURCE 86
105#define CSI_INTR_SOURCE 87
106#define DSI_INTR_SOURCE 88
107#define GMII_PHY_INTR_SOURCE 89
108#define LPI_INTR_SOURCE 90
109#define PMT_INTR_SOURCE 91
110#define ETH_MAC_INTR_SOURCE 92
111#define USB_OTG_INTR_SOURCE 93
112#define USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE 94
113#define JPEG_INTR_SOURCE 95
114#define PPA_INTR_SOURCE 96
115#define CORE0_TRACE_INTR_SOURCE 97
116#define CORE1_TRACE_INTR_SOURCE 98
117#define HP_CORE_CTRL_INTR_SOURCE 99
118#define ISP_INTR_SOURCE 100
119#define I3C_MST_INTR_SOURCE 101
120#define I3C_SLV_INTR_SOURCE 102
121#define USB_OTG11_CH0_INTR_SOURCE 103
122#define DMA2D_IN_CH0_INTR_SOURCE 104
123#define DMA2D_IN_CH1_INTR_SOURCE 105
124#define DMA2D_OUT_CH0_INTR_SOURCE 106
125#define DMA2D_OUT_CH1_INTR_SOURCE 107
126#define DMA2D_OUT_CH2_INTR_SOURCE 108
127#define PSRAM_MSPI_INTR_SOURCE 109
128#define HP_SYSREG_INTR_SOURCE 110
129#define PCNT_INTR_SOURCE 111
130#define HP_PAU_INTR_SOURCE 112
131#define HP_PARLIO_RX_INTR_SOURCE 113
132#define HP_PARLIO_TX_INTR_SOURCE 114
133#define ASSIST_DEBUG_INTR_SOURCE 120
134
140#define IRQ_DEFAULT_PRIORITY 0
141
142#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32P4_INTMUX_H_ */