Zephyr API Documentation 4.4.0-rc1
A Scalable Open Source RTOS
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esp32c5_clock.h
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1/*
2 * Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
11
12#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C5_H_
13#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C5_H_
14
15/* Supported CPU clock Sources */
16#define ESP32_CPU_CLK_SRC_XTAL 0U
17#define ESP32_CPU_CLK_SRC_PLL 1U
18#define ESP32_CLK_SRC_RC_FAST 2U
19
20/* Supported CPU frequencies */
21#define ESP32_CLK_CPU_PLL_80M 80000000
22#define ESP32_CLK_CPU_PLL_160M 160000000
23#define ESP32_CLK_CPU_PLL_240M 240000000
24#define ESP32_CLK_CPU_RC_FAST_FREQ 17500000
25
26/* Supported XTAL Frequencies */
27#define ESP32_CLK_XTAL_40M 40000000
28#define ESP32_CLK_XTAL_48M 48000000
29
30/* Supported RTC fast clock sources */
31#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
32#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
33#define ESP32_RTC_FAST_CLK_SRC_XTAL 2
34
35/* Supported RTC slow clock sources */
36#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
37#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
38#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW 3
39#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
40
41/* RTC slow clock frequencies */
42#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
43#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
44#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ 32768
45
46/* Shared module IDs - must match shared_periph_module_t enum in periph_defs.h
47 * These are used by the clock control driver to identify peripheral modules.
48 */
49#define ESP32_TIMG0_MODULE 0
50#define ESP32_TIMG1_MODULE 1
51#define ESP32_UHCI0_MODULE 2
52#define ESP32_SYSTIMER_MODULE 3
53/* Peripherals clock managed by the modem_clock driver must be listed last */
54#define ESP32_WIFI_MODULE 4
55#define ESP32_BT_MODULE 5
56#define ESP32_IEEE802154_MODULE 6
57#define ESP32_COEX_MODULE 7
58#define ESP32_PHY_MODULE 8
59#define ESP32_ANA_I2C_MASTER_MODULE 9
60#define ESP32_MODEM_ETM_MODULE 10
61#define ESP32_MODEM_ADC_COMMON_FE_MODULE 11
62#define ESP32_MODULE_MAX 13
63
64/* Non-shared peripherals - these have dedicated clock control in their drivers
65 * and don't use periph_module_enable(). Values start at 100.
66 */
67#define ESP32_LEDC_MODULE 100
68#define ESP32_UART0_MODULE 101
69#define ESP32_UART1_MODULE 102
70#define ESP32_USB_MODULE 103
71#define ESP32_I2C0_MODULE 104
72#define ESP32_I2S0_MODULE 105
73#define ESP32_RMT_MODULE 106
74#define ESP32_PCNT_MODULE 107
75#define ESP32_SPI_MODULE 108
76#define ESP32_SPI2_MODULE 109
77#define ESP32_TWAI0_MODULE 110
78#define ESP32_TWAI1_MODULE 111
79#define ESP32_RNG_MODULE 112
80#define ESP32_GDMA_MODULE 113
81#define ESP32_MCPWM0_MODULE 114
82#define ESP32_ETM_MODULE 115
83#define ESP32_PARLIO_MODULE 116
84#define ESP32_TEMPSENSOR_MODULE 117
85#define ESP32_SARADC_MODULE 118
86#define ESP32_RSA_MODULE 119
87#define ESP32_AES_MODULE 120
88#define ESP32_SHA_MODULE 121
89#define ESP32_ECC_MODULE 122
90#define ESP32_HMAC_MODULE 123
91#define ESP32_DS_MODULE 124
92#define ESP32_SDIO_SLAVE_MODULE 125
93#define ESP32_ASSIST_DEBUG_MODULE 126
94/* LP peripherals */
95#define ESP32_LP_I2C0_MODULE 127
96#define ESP32_LP_UART0_MODULE 128
97
98#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C5_H_ */