Zephyr API Documentation
4.0.0-rc3
A Scalable Open Source RTOS
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esp32s3-xtensa-intmux.h
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/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_
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#define WIFI_MAC_INTR_SOURCE 0
/* interrupt of WiFi MAC, level*/
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#define WIFI_MAC_NMI_SOURCE 1
/* interrupt of WiFi MAC, NMI */
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#define WIFI_PWR_INTR_SOURCE 2
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#define WIFI_BB_INTR_SOURCE 3
/* interrupt of WiFi BB, level*/
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#define BT_MAC_INTR_SOURCE 4
/* will be cancelled*/
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#define BT_BB_INTR_SOURCE 5
/* interrupt of BT BB, level*/
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#define BT_BB_NMI_SOURCE 6
/* interrupt of BT BB, NMI*/
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#define RWBT_INTR_SOURCE 7
/* interrupt of RWBT, level*/
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#define RWBLE_INTR_SOURCE 8
/* interrupt of RWBLE, level*/
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#define RWBT_NMI_SOURCE 9
/* interrupt of RWBT, NMI*/
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#define RWBLE_NMI_SOURCE 10
/* interrupt of RWBLE, NMI*/
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#define I2C_MASTER_SOURCE 11
/* interrupt of I2C Master, level*/
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#define SLC0_INTR_SOURCE 12
/* interrupt of SLC0, level*/
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#define SLC1_INTR_SOURCE 13
/* interrupt of SLC1, level*/
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#define UHCI0_INTR_SOURCE 14
/* interrupt of UHCI0, level*/
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#define UHCI1_INTR_SOURCE 15
/* interrupt of UHCI1, level*/
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#define GPIO_INTR_SOURCE 16
/* interrupt of GPIO, level*/
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#define GPIO_NMI_SOURCE 17
/* interrupt of GPIO, NMI*/
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#define GPIO_INTR_SOURCE2 18
/* interrupt of GPIO, level*/
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#define GPIO_NMI_SOURCE2 19
/* interrupt of GPIO, NMI*/
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#define SPI1_INTR_SOURCE 20
/* interrupt of SPI1, level*/
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#define SPI2_INTR_SOURCE 21
/* interrupt of SPI2, level*/
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#define SPI3_INTR_SOURCE 22
/* interrupt of SPI3, level*/
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#define LCD_CAM_INTR_SOURCE 24
/* interrupt of LCD camera, level*/
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#define I2S0_INTR_SOURCE 25
/* interrupt of I2S0, level*/
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#define I2S1_INTR_SOURCE 26
/* interrupt of I2S1, level*/
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#define UART0_INTR_SOURCE 27
/* interrupt of UART0, level*/
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#define UART1_INTR_SOURCE 28
/* interrupt of UART1, level*/
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#define UART2_INTR_SOURCE 29
/* interrupt of UART2, level*/
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#define SDIO_HOST_INTR_SOURCE 30
/* interrupt of SD/SDIO/MMC HOST, level*/
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#define PWM0_INTR_SOURCE 31
/* interrupt of PWM0, level, Reserved*/
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#define PWM1_INTR_SOURCE 32
/* interrupt of PWM1, level, Reserved*/
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#define LEDC_INTR_SOURCE 35
/* interrupt of LED PWM, level*/
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#define EFUSE_INTR_SOURCE 36
/* interrupt of efuse, level, not likely to use*/
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#define TWAI_INTR_SOURCE 37
/* interrupt of can, level*/
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#define USB_INTR_SOURCE 38
/* interrupt of USB, level*/
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#define RTC_CORE_INTR_SOURCE 39
/* interrupt of rtc core and watchdog, level*/
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#define RMT_INTR_SOURCE 40
/* interrupt of remote controller, level*/
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#define PCNT_INTR_SOURCE 41
/* interrupt of pulse count, level*/
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#define I2C_EXT0_INTR_SOURCE 42
/* interrupt of I2C controller1, level*/
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#define I2C_EXT1_INTR_SOURCE 43
/* interrupt of I2C controller0, level*/
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#define SPI2_DMA_INTR_SOURCE 44
/* interrupt of SPI2 DMA, level*/
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#define SPI3_DMA_INTR_SOURCE 45
/* interrupt of SPI3 DMA, level*/
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#define WDT_INTR_SOURCE 47
/* will be cancelled*/
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#define TIMER1_INTR_SOURCE 48
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#define TIMER2_INTR_SOURCE 49
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#define TG0_T0_LEVEL_INTR_SOURCE 50
/* interrupt of TIMER_GROUP0, TIMER0, EDGE*/
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#define TG0_T1_LEVEL_INTR_SOURCE 51
/* interrupt of TIMER_GROUP0, TIMER1, EDGE*/
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#define TG0_WDT_LEVEL_INTR_SOURCE 52
/* interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
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#define TG1_T0_LEVEL_INTR_SOURCE 53
/* interrupt of TIMER_GROUP1, TIMER0, EDGE*/
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#define TG1_T1_LEVEL_INTR_SOURCE 54
/* interrupt of TIMER_GROUP1, TIMER1, EDGE*/
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#define TG1_WDT_LEVEL_INTR_SOURCE 55
/* interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
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#define CACHE_IA_INTR_SOURCE 56
/* interrupt of Cache Invalid Access, LEVEL*/
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#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 57
/* interrupt of system timer 0, EDGE*/
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#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 58
/* interrupt of system timer 1, EDGE*/
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#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 59
/* interrupt of system timer 2, EDGE*/
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#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 60
/* interrupt of SPI0/SPI1 Cache/Rejected, LEVEL*/
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#define DCACHE_PRELOAD0_INTR_SOURCE 61
/* interrupt of DCache preload operation, LEVEL*/
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#define ICACHE_PRELOAD0_INTR_SOURCE 62
/* interrupt of ICache perload operation, LEVEL*/
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#define DCACHE_SYNC0_INTR_SOURCE 63
/* interrupt of data cache sync done, LEVEL*/
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#define ICACHE_SYNC0_INTR_SOURCE 64
/* interrupt of instr. cache sync done, LEVEL*/
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#define APB_ADC_INTR_SOURCE 65
/* interrupt of APB ADC, LEVEL*/
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#define DMA_IN_CH0_INTR_SOURCE 66
/* interrupt of general DMA RX channel 0, LEVEL*/
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#define DMA_IN_CH1_INTR_SOURCE 67
/* interrupt of general DMA RX channel 1, LEVEL*/
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#define DMA_IN_CH2_INTR_SOURCE 68
/* interrupt of general DMA RX channel 2, LEVEL*/
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#define DMA_IN_CH3_INTR_SOURCE 69
/* interrupt of general DMA RX channel 3, LEVEL*/
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#define DMA_IN_CH4_INTR_SOURCE 70
/* interrupt of general DMA RX channel 4, LEVEL*/
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#define DMA_OUT_CH0_INTR_SOURCE 71
/* interrupt of general DMA TX channel 0, LEVEL*/
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#define DMA_OUT_CH1_INTR_SOURCE 72
/* interrupt of general DMA TX channel 1, LEVEL*/
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#define DMA_OUT_CH2_INTR_SOURCE 73
/* interrupt of general DMA TX channel 2, LEVEL*/
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#define DMA_OUT_CH3_INTR_SOURCE 74
/* interrupt of general DMA TX channel 3, LEVEL*/
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#define DMA_OUT_CH4_INTR_SOURCE 75
/* interrupt of general DMA TX channel 4, LEVEL*/
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#define RSA_INTR_SOURCE 76
/* interrupt of RSA accelerator, level*/
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#define AES_INTR_SOURCE 77
/* interrupt of AES accelerator, level*/
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#define SHA_INTR_SOURCE 78
/* interrupt of SHA accelerator, level*/
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#define FROM_CPU_INTR0_SOURCE 79
/* interrupt0 generated from a CPU, level*/
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#define FROM_CPU_INTR1_SOURCE 80
/* interrupt1 generated from a CPU, level*/
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#define FROM_CPU_INTR2_SOURCE 81
/* interrupt2 generated from a CPU, level*/
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#define FROM_CPU_INTR3_SOURCE 82
/* interrupt3 generated from a CPU, level*/
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#define ASSIST_DEBUG_INTR_SOURCE 83
/* interrupt of Assist debug module, LEVEL*/
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#define DMA_APBPERI_PMS_INTR_SOURCE 84
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#define CORE0_IRAM0_PMS_INTR_SOURCE 85
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#define CORE0_DRAM0_PMS_INTR_SOURCE 86
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#define CORE0_PIF_PMS_INTR_SOURCE 87
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#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 88
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#define CORE1_IRAM0_PMS_INTR_SOURCE 89
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#define CORE1_DRAM0_PMS_INTR_SOURCE 90
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#define CORE1_PIF_PMS_INTR_SOURCE 91
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#define CORE1_PIF_PMS_SIZE_INTR_SOURCE 92
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#define BACKUP_PMS_VIOLATE_INTR_SOURCE 93
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#define CACHE_CORE0_ACS_INTR_SOURCE 94
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#define CACHE_CORE1_ACS_INTR_SOURCE 95
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#define USB_SERIAL_JTAG_INTR_SOURCE 96
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#define PREI_BACKUP_INTR_SOURCE 97
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#define DMA_EXTMEM_REJECT_SOURCE 98
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#define MAX_INTR_SOURCE 99
/* number of interrupt sources */
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/* For Xtensa architecture, zero will allocate low/medium
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* levels of priority (ESP_INTR_FLAG_LOWMED)
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*/
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#define IRQ_DEFAULT_PRIORITY 0
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#define ESP_INTR_FLAG_SHARED (1<<8)
/* Interrupt can be shared between ISRs */
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#endif
zephyr
dt-bindings
interrupt-controller
esp32s3-xtensa-intmux.h
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