Zephyr API Documentation 4.4.99
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ADS1220 ADC driver API
Device Drivers » ADC

ADS1220 ADC driver API. More...

Macros

#define ADS1220_RESOLUTION   24u
 ADC resolution in bits.
#define ADS1220_CHANNELS   4u
 Number of input channels.
#define ADS1220_CHANNEL_ID   0x00u
 Device ID register value.
#define ADS1220_REG0_MUX_MSK   0xF0u
 Mask for MUX field in configuration register 0.
#define ADS1220_REG0_MUX_AIN0_AIN1   (0x0u << 0x04)
 MUX: AINP=AIN0, AINN=AIN1.
#define ADS1220_REG0_MUX_AIN0_AIN2   (0x1u << 0x04)
 MUX: AINP=AIN0, AINN=AIN2.
#define ADS1220_REG0_MUX_AIN0_AIN3   (0x2u << 0x04)
 MUX: AINP=AIN0, AINN=AIN3.
#define ADS1220_REG0_MUX_AIN1_AIN2   (0x3u << 0x04)
 MUX: AINP=AIN1, AINN=AIN2.
#define ADS1220_REG0_MUX_AIN1_AIN3   (0x4u << 0x04)
 MUX: AINP=AIN1, AINN=AIN3.
#define ADS1220_REG0_MUX_AIN2_AIN3   (0x5u << 0x04)
 MUX: AINP=AIN2, AINN=AIN3.
#define ADS1220_REG0_MUX_AIN1_AIN0   (0x6u << 0x04)
 MUX: AINP=AIN1, AINN=AIN0.
#define ADS1220_REG0_MUX_AIN3_AIN2   (0x7u << 0x04)
 MUX: AINP=AIN3, AINN=AIN2.
#define ADS1220_REG0_MUX_AIN0_AVSS   (0x8u << 0x04)
 MUX: AINP=AIN0, AINN=AVSS.
#define ADS1220_REG0_MUX_AIN1_AVSS   (0x9u << 0x04)
 MUX: AINP=AIN1, AINN=AVSS.
#define ADS1220_REG0_MUX_AIN2_AVSS   (0xAu << 0x04)
 MUX: AINP=AIN2, AINN=AVSS.
#define ADS1220_REG0_MUX_AIN3_AVSS   (0xBu << 0x04)
 MUX: AINP=AIN3, AINN=AVSS.
#define ADS1220_REG0_MUX_V_REF   (0xCu << 0x04)
 MUX: (V_REFPx - V_REFNx) / 4 monitor.
#define ADS1220_REG0_MUX_AVDD_AVSS_1   (0xDu << 0x04)
 MUX: (AVDD - AVSS) / 4 monitor.
#define ADS1220_REG0_MUX_AVDD_AVSS_2   (0xEu << 0x04)
 MUX: AINP and AINN shorted to (AVDD + AVSS) / 2.
#define ADS1220_REG0_MUX_RESERVED   (0xFu << 0x04)
 MUX: Reserved.
#define ADS1220_REG0_GAIN_MSK   0x0Eu
 Mask for GAIN field in configuration register 0.
#define ADS1220_REG0_GAIN_1   (0x0u << 0x01)
 PGA gain = 1.
#define ADS1220_REG0_GAIN_2   (0x1u << 0x01)
 PGA gain = 2.
#define ADS1220_REG0_GAIN_4   (0x2u << 0x01)
 PGA gain = 4.
#define ADS1220_REG0_GAIN_8   (0x3u << 0x01)
 PGA gain = 8.
#define ADS1220_REG0_GAIN_16   (0x4u << 0x01)
 PGA gain = 16.
#define ADS1220_REG0_GAIN_32   (0x5u << 0x01)
 PGA gain = 32.
#define ADS1220_REG0_GAIN_64   (0x6u << 0x01)
 PGA gain = 64.
#define ADS1220_REG0_GAIN_128   (0x7u << 0x01)
 PGA gain = 128.
#define ADS1220_REG0_PGA_BYPASS   BIT(0)
 PGA bypass bit in configuration register 0.
#define ADS1220_REG1_DR_MSK   0xE0u
 Mask for DR field in configuration register 1.
#define ADS1220_REG1_DR_POS   0x5u
 Bit position of DR field in configuration register 1.
#define ADS1220_REG1_MODE_MSK   0x18u
 Mask for MODE field in configuration register 1.
#define ADS1220_REG1_MODE_POS   0x3u
 Bit position of MODE field in configuration register 1.
#define ADS1220_REG1_MODE_NORMAL   (0x0u << 0x03)
 Operating mode: normal.
#define ADS1220_REG1_MODE_DUTY_CYCLE   (0x1u << 0x03)
 Operating mode: duty-cycle.
#define ADS1220_REG1_MODE_TURBO   (0x2u << 0x03)
 Operating mode: turbo.
#define ADS1220_REG1_CM   BIT(2)
 Conversion mode bit in configuration register 1.
#define ADS1220_REG1_TS   BIT(1)
 Temperature sensor mode bit in configuration register 1.
#define ADS1220_REG1_BCS   BIT(0)
 Burn-out current sources bit in configuration register 1.
#define ADS1220_REG2_VREF_MSK   0xC0u
 Mask for VREF field in configuration register 2.
#define ADS1220_REG2_VREF_INT   (0x0u << 0x06)
 VREF: internal 2.048V reference.
#define ADS1220_REG2_VREF_EXT_0   (0x1u << 0x06)
 VREF: external reference 0 (REFP0/REFN0).
#define ADS1220_REG2_VREF_EXT_1   (0x2u << 0x06)
 VREF: external reference 1 (REFP1/REFN1).
#define ADS1220_REG2_VREF_SUPPLY   (0x3u << 0x06)
 VREF: analog supply (AVDD - AVSS).
#define ADS1220_REG2_50_60HZ_MSK   0x30u
 Mask for 50/60Hz rejection filter in configuration register 2.
#define ADS1220_REG2_50_60HZ_NONE   (0x0u << 0x04)
 50/60Hz filter: no rejection
#define ADS1220_REG2_50_60HZ_50HZ   (0x1u << 0x04)
 50/60Hz filter: reject 50Hz only
#define ADS1220_REG2_50_60HZ_60HZ   (0x2u << 0x04)
 50/60Hz filter: reject 60Hz only
#define ADS1220_REG2_50_60HZ_BOTH   (0x3u << 0x04)
 50/60Hz filter: reject both 50Hz and 60Hz
#define ADS1220_REG2_PSW   BIT(3)
 Low-side power switch bit in configuration register 2.
#define ADS1220_REG2_IDAC_MSK   0x07u
 Mask for IDAC current field in configuration register 2.
#define ADS1220_REG2_IDAC_OFF   (0x0u)
 IDAC current: off.
#define ADS1220_REG2_IDAC_10UA   (0x1u)
 IDAC current: 10 uA.
#define ADS1220_REG2_IDAC_50UA   (0x2u)
 IDAC current: 50 uA.
#define ADS1220_REG2_IDAC_100UA   (0x3u)
 IDAC current: 100 uA.
#define ADS1220_REG2_IDAC_250UA   (0x4u)
 IDAC current: 250 uA.
#define ADS1220_REG2_IDAC_500UA   (0x5u)
 IDAC current: 500 uA.
#define ADS1220_REG2_IDAC_1000UA   (0x6u)
 IDAC current: 1000 uA.
#define ADS1220_REG2_IDAC_1500UA   (0x7u)
 IDAC current: 1500 uA.
#define ADS1220_REG3_I1MUX_MSK   0xE0u
 Mask for I1MUX field in configuration register 3.
#define ADS1220_REG3_I1MUX_POS   0x5u
 Bit position of I1MUX field in configuration register 3.
#define ADS1220_REG3_I1MUX_DISABLED   (0x0u << 0x05)
 I1MUX: IDAC1 disabled.
#define ADS1220_REG3_I1MUX_AIN0_REFP1   (0x1u << 0x05)
 I1MUX: IDAC1 connected to AIN0/REFP1.
#define ADS1220_REG3_I1MUX_AIN1   (0x2u << 0x05)
 I1MUX: IDAC1 connected to AIN1.
#define ADS1220_REG3_I1MUX_AIN2   (0x3u << 0x05)
 I1MUX: IDAC1 connected to AIN2.
#define ADS1220_REG3_I1MUX_AIN3_REFN1   (0x4u << 0x05)
 I1MUX: IDAC1 connected to AIN3/REFN1.
#define ADS1220_REG3_I1MUX_REFP   (0x5u << 0x05)
 I1MUX: IDAC1 connected to REFP0.
#define ADS1220_REG3_I1MUX_REFN   (0x6u << 0x05)
 I1MUX: IDAC1 connected to REFN0.
#define ADS1220_REG3_I2MUX_MSK   0x1Cu
 Mask for I2MUX field in configuration register 3.
#define ADS1220_REG3_I2MUX_POS   0x2u
 Bit position of I2MUX field in configuration register 3.
#define ADS1220_REG3_I2MUX_DISABLED   (0x0u << 0x02)
 I2MUX: IDAC2 disabled.
#define ADS1220_REG3_I2MUX_AIN0_REFP1   (0x1u << 0x02)
 I2MUX: IDAC2 connected to AIN0/REFP1.
#define ADS1220_REG3_I2MUX_AIN1   (0x2u << 0x02)
 I2MUX: IDAC2 connected to AIN1.
#define ADS1220_REG3_I2MUX_AIN2   (0x3u << 0x02)
 I2MUX: IDAC2 connected to AIN2.
#define ADS1220_REG3_I2MUX_AIN3_REFN1   (0x4u << 0x02)
 I2MUX: IDAC2 connected to AIN3/REFN1.
#define ADS1220_REG3_I2MUX_REFP   (0x5u << 0x02)
 I2MUX: IDAC2 connected to REFP0.
#define ADS1220_REG3_I2MUX_REFN   (0x6u << 0x02)
 I2MUX: IDAC2 connected to REFN0.
#define ADS1220_REG3_DRDYM   BIT(1)
 DRDY mode bit in configuration register 3.
#define ADS1220_REG3_RESERVED   BIT(0)
 Reserved bit in configuration register 3.

Detailed Description

ADS1220 ADC driver API.

Macro Definition Documentation

◆ ADS1220_CHANNEL_ID

#define ADS1220_CHANNEL_ID   0x00u

#include <zephyr/drivers/adc/ads1220.h>

Device ID register value.

◆ ADS1220_CHANNELS

#define ADS1220_CHANNELS   4u

#include <zephyr/drivers/adc/ads1220.h>

Number of input channels.

◆ ADS1220_REG0_GAIN_1

#define ADS1220_REG0_GAIN_1   (0x0u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 1.

◆ ADS1220_REG0_GAIN_128

#define ADS1220_REG0_GAIN_128   (0x7u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 128.

◆ ADS1220_REG0_GAIN_16

#define ADS1220_REG0_GAIN_16   (0x4u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 16.

◆ ADS1220_REG0_GAIN_2

#define ADS1220_REG0_GAIN_2   (0x1u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 2.

◆ ADS1220_REG0_GAIN_32

#define ADS1220_REG0_GAIN_32   (0x5u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 32.

◆ ADS1220_REG0_GAIN_4

#define ADS1220_REG0_GAIN_4   (0x2u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 4.

◆ ADS1220_REG0_GAIN_64

#define ADS1220_REG0_GAIN_64   (0x6u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 64.

◆ ADS1220_REG0_GAIN_8

#define ADS1220_REG0_GAIN_8   (0x3u << 0x01)

#include <zephyr/drivers/adc/ads1220.h>

PGA gain = 8.

◆ ADS1220_REG0_GAIN_MSK

#define ADS1220_REG0_GAIN_MSK   0x0Eu

#include <zephyr/drivers/adc/ads1220.h>

Mask for GAIN field in configuration register 0.

◆ ADS1220_REG0_MUX_AIN0_AIN1

#define ADS1220_REG0_MUX_AIN0_AIN1   (0x0u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN0, AINN=AIN1.

◆ ADS1220_REG0_MUX_AIN0_AIN2

#define ADS1220_REG0_MUX_AIN0_AIN2   (0x1u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN0, AINN=AIN2.

◆ ADS1220_REG0_MUX_AIN0_AIN3

#define ADS1220_REG0_MUX_AIN0_AIN3   (0x2u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN0, AINN=AIN3.

◆ ADS1220_REG0_MUX_AIN0_AVSS

#define ADS1220_REG0_MUX_AIN0_AVSS   (0x8u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN0, AINN=AVSS.

◆ ADS1220_REG0_MUX_AIN1_AIN0

#define ADS1220_REG0_MUX_AIN1_AIN0   (0x6u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN1, AINN=AIN0.

◆ ADS1220_REG0_MUX_AIN1_AIN2

#define ADS1220_REG0_MUX_AIN1_AIN2   (0x3u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN1, AINN=AIN2.

◆ ADS1220_REG0_MUX_AIN1_AIN3

#define ADS1220_REG0_MUX_AIN1_AIN3   (0x4u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN1, AINN=AIN3.

◆ ADS1220_REG0_MUX_AIN1_AVSS

#define ADS1220_REG0_MUX_AIN1_AVSS   (0x9u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN1, AINN=AVSS.

◆ ADS1220_REG0_MUX_AIN2_AIN3

#define ADS1220_REG0_MUX_AIN2_AIN3   (0x5u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN2, AINN=AIN3.

◆ ADS1220_REG0_MUX_AIN2_AVSS

#define ADS1220_REG0_MUX_AIN2_AVSS   (0xAu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN2, AINN=AVSS.

◆ ADS1220_REG0_MUX_AIN3_AIN2

#define ADS1220_REG0_MUX_AIN3_AIN2   (0x7u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN3, AINN=AIN2.

◆ ADS1220_REG0_MUX_AIN3_AVSS

#define ADS1220_REG0_MUX_AIN3_AVSS   (0xBu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP=AIN3, AINN=AVSS.

◆ ADS1220_REG0_MUX_AVDD_AVSS_1

#define ADS1220_REG0_MUX_AVDD_AVSS_1   (0xDu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: (AVDD - AVSS) / 4 monitor.

◆ ADS1220_REG0_MUX_AVDD_AVSS_2

#define ADS1220_REG0_MUX_AVDD_AVSS_2   (0xEu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: AINP and AINN shorted to (AVDD + AVSS) / 2.

◆ ADS1220_REG0_MUX_MSK

#define ADS1220_REG0_MUX_MSK   0xF0u

#include <zephyr/drivers/adc/ads1220.h>

Mask for MUX field in configuration register 0.

◆ ADS1220_REG0_MUX_RESERVED

#define ADS1220_REG0_MUX_RESERVED   (0xFu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: Reserved.

◆ ADS1220_REG0_MUX_V_REF

#define ADS1220_REG0_MUX_V_REF   (0xCu << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

MUX: (V_REFPx - V_REFNx) / 4 monitor.

◆ ADS1220_REG0_PGA_BYPASS

#define ADS1220_REG0_PGA_BYPASS   BIT(0)

#include <zephyr/drivers/adc/ads1220.h>

PGA bypass bit in configuration register 0.

◆ ADS1220_REG1_BCS

#define ADS1220_REG1_BCS   BIT(0)

#include <zephyr/drivers/adc/ads1220.h>

Burn-out current sources bit in configuration register 1.

◆ ADS1220_REG1_CM

#define ADS1220_REG1_CM   BIT(2)

#include <zephyr/drivers/adc/ads1220.h>

Conversion mode bit in configuration register 1.

◆ ADS1220_REG1_DR_MSK

#define ADS1220_REG1_DR_MSK   0xE0u

#include <zephyr/drivers/adc/ads1220.h>

Mask for DR field in configuration register 1.

◆ ADS1220_REG1_DR_POS

#define ADS1220_REG1_DR_POS   0x5u

#include <zephyr/drivers/adc/ads1220.h>

Bit position of DR field in configuration register 1.

◆ ADS1220_REG1_MODE_DUTY_CYCLE

#define ADS1220_REG1_MODE_DUTY_CYCLE   (0x1u << 0x03)

#include <zephyr/drivers/adc/ads1220.h>

Operating mode: duty-cycle.

◆ ADS1220_REG1_MODE_MSK

#define ADS1220_REG1_MODE_MSK   0x18u

#include <zephyr/drivers/adc/ads1220.h>

Mask for MODE field in configuration register 1.

◆ ADS1220_REG1_MODE_NORMAL

#define ADS1220_REG1_MODE_NORMAL   (0x0u << 0x03)

#include <zephyr/drivers/adc/ads1220.h>

Operating mode: normal.

◆ ADS1220_REG1_MODE_POS

#define ADS1220_REG1_MODE_POS   0x3u

#include <zephyr/drivers/adc/ads1220.h>

Bit position of MODE field in configuration register 1.

◆ ADS1220_REG1_MODE_TURBO

#define ADS1220_REG1_MODE_TURBO   (0x2u << 0x03)

#include <zephyr/drivers/adc/ads1220.h>

Operating mode: turbo.

◆ ADS1220_REG1_TS

#define ADS1220_REG1_TS   BIT(1)

#include <zephyr/drivers/adc/ads1220.h>

Temperature sensor mode bit in configuration register 1.

◆ ADS1220_REG2_50_60HZ_50HZ

#define ADS1220_REG2_50_60HZ_50HZ   (0x1u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

50/60Hz filter: reject 50Hz only

◆ ADS1220_REG2_50_60HZ_60HZ

#define ADS1220_REG2_50_60HZ_60HZ   (0x2u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

50/60Hz filter: reject 60Hz only

◆ ADS1220_REG2_50_60HZ_BOTH

#define ADS1220_REG2_50_60HZ_BOTH   (0x3u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

50/60Hz filter: reject both 50Hz and 60Hz

◆ ADS1220_REG2_50_60HZ_MSK

#define ADS1220_REG2_50_60HZ_MSK   0x30u

#include <zephyr/drivers/adc/ads1220.h>

Mask for 50/60Hz rejection filter in configuration register 2.

◆ ADS1220_REG2_50_60HZ_NONE

#define ADS1220_REG2_50_60HZ_NONE   (0x0u << 0x04)

#include <zephyr/drivers/adc/ads1220.h>

50/60Hz filter: no rejection

◆ ADS1220_REG2_IDAC_1000UA

#define ADS1220_REG2_IDAC_1000UA   (0x6u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 1000 uA.

◆ ADS1220_REG2_IDAC_100UA

#define ADS1220_REG2_IDAC_100UA   (0x3u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 100 uA.

◆ ADS1220_REG2_IDAC_10UA

#define ADS1220_REG2_IDAC_10UA   (0x1u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 10 uA.

◆ ADS1220_REG2_IDAC_1500UA

#define ADS1220_REG2_IDAC_1500UA   (0x7u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 1500 uA.

◆ ADS1220_REG2_IDAC_250UA

#define ADS1220_REG2_IDAC_250UA   (0x4u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 250 uA.

◆ ADS1220_REG2_IDAC_500UA

#define ADS1220_REG2_IDAC_500UA   (0x5u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 500 uA.

◆ ADS1220_REG2_IDAC_50UA

#define ADS1220_REG2_IDAC_50UA   (0x2u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: 50 uA.

◆ ADS1220_REG2_IDAC_MSK

#define ADS1220_REG2_IDAC_MSK   0x07u

#include <zephyr/drivers/adc/ads1220.h>

Mask for IDAC current field in configuration register 2.

◆ ADS1220_REG2_IDAC_OFF

#define ADS1220_REG2_IDAC_OFF   (0x0u)

#include <zephyr/drivers/adc/ads1220.h>

IDAC current: off.

◆ ADS1220_REG2_PSW

#define ADS1220_REG2_PSW   BIT(3)

#include <zephyr/drivers/adc/ads1220.h>

Low-side power switch bit in configuration register 2.

◆ ADS1220_REG2_VREF_EXT_0

#define ADS1220_REG2_VREF_EXT_0   (0x1u << 0x06)

#include <zephyr/drivers/adc/ads1220.h>

VREF: external reference 0 (REFP0/REFN0).

◆ ADS1220_REG2_VREF_EXT_1

#define ADS1220_REG2_VREF_EXT_1   (0x2u << 0x06)

#include <zephyr/drivers/adc/ads1220.h>

VREF: external reference 1 (REFP1/REFN1).

◆ ADS1220_REG2_VREF_INT

#define ADS1220_REG2_VREF_INT   (0x0u << 0x06)

#include <zephyr/drivers/adc/ads1220.h>

VREF: internal 2.048V reference.

◆ ADS1220_REG2_VREF_MSK

#define ADS1220_REG2_VREF_MSK   0xC0u

#include <zephyr/drivers/adc/ads1220.h>

Mask for VREF field in configuration register 2.

◆ ADS1220_REG2_VREF_SUPPLY

#define ADS1220_REG2_VREF_SUPPLY   (0x3u << 0x06)

#include <zephyr/drivers/adc/ads1220.h>

VREF: analog supply (AVDD - AVSS).

◆ ADS1220_REG3_DRDYM

#define ADS1220_REG3_DRDYM   BIT(1)

#include <zephyr/drivers/adc/ads1220.h>

DRDY mode bit in configuration register 3.

◆ ADS1220_REG3_I1MUX_AIN0_REFP1

#define ADS1220_REG3_I1MUX_AIN0_REFP1   (0x1u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to AIN0/REFP1.

◆ ADS1220_REG3_I1MUX_AIN1

#define ADS1220_REG3_I1MUX_AIN1   (0x2u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to AIN1.

◆ ADS1220_REG3_I1MUX_AIN2

#define ADS1220_REG3_I1MUX_AIN2   (0x3u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to AIN2.

◆ ADS1220_REG3_I1MUX_AIN3_REFN1

#define ADS1220_REG3_I1MUX_AIN3_REFN1   (0x4u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to AIN3/REFN1.

◆ ADS1220_REG3_I1MUX_DISABLED

#define ADS1220_REG3_I1MUX_DISABLED   (0x0u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 disabled.

◆ ADS1220_REG3_I1MUX_MSK

#define ADS1220_REG3_I1MUX_MSK   0xE0u

#include <zephyr/drivers/adc/ads1220.h>

Mask for I1MUX field in configuration register 3.

◆ ADS1220_REG3_I1MUX_POS

#define ADS1220_REG3_I1MUX_POS   0x5u

#include <zephyr/drivers/adc/ads1220.h>

Bit position of I1MUX field in configuration register 3.

◆ ADS1220_REG3_I1MUX_REFN

#define ADS1220_REG3_I1MUX_REFN   (0x6u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to REFN0.

◆ ADS1220_REG3_I1MUX_REFP

#define ADS1220_REG3_I1MUX_REFP   (0x5u << 0x05)

#include <zephyr/drivers/adc/ads1220.h>

I1MUX: IDAC1 connected to REFP0.

◆ ADS1220_REG3_I2MUX_AIN0_REFP1

#define ADS1220_REG3_I2MUX_AIN0_REFP1   (0x1u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to AIN0/REFP1.

◆ ADS1220_REG3_I2MUX_AIN1

#define ADS1220_REG3_I2MUX_AIN1   (0x2u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to AIN1.

◆ ADS1220_REG3_I2MUX_AIN2

#define ADS1220_REG3_I2MUX_AIN2   (0x3u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to AIN2.

◆ ADS1220_REG3_I2MUX_AIN3_REFN1

#define ADS1220_REG3_I2MUX_AIN3_REFN1   (0x4u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to AIN3/REFN1.

◆ ADS1220_REG3_I2MUX_DISABLED

#define ADS1220_REG3_I2MUX_DISABLED   (0x0u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 disabled.

◆ ADS1220_REG3_I2MUX_MSK

#define ADS1220_REG3_I2MUX_MSK   0x1Cu

#include <zephyr/drivers/adc/ads1220.h>

Mask for I2MUX field in configuration register 3.

◆ ADS1220_REG3_I2MUX_POS

#define ADS1220_REG3_I2MUX_POS   0x2u

#include <zephyr/drivers/adc/ads1220.h>

Bit position of I2MUX field in configuration register 3.

◆ ADS1220_REG3_I2MUX_REFN

#define ADS1220_REG3_I2MUX_REFN   (0x6u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to REFN0.

◆ ADS1220_REG3_I2MUX_REFP

#define ADS1220_REG3_I2MUX_REFP   (0x5u << 0x02)

#include <zephyr/drivers/adc/ads1220.h>

I2MUX: IDAC2 connected to REFP0.

◆ ADS1220_REG3_RESERVED

#define ADS1220_REG3_RESERVED   BIT(0)

#include <zephyr/drivers/adc/ads1220.h>

Reserved bit in configuration register 3.

◆ ADS1220_RESOLUTION

#define ADS1220_RESOLUTION   24u

#include <zephyr/drivers/adc/ads1220.h>

ADC resolution in bits.