Microchip SAM D5x/E5x

Files
file	mchp_clock_sam_d5x_e5x.h
	Clock control header file for the Microchip SAM D5x/E5x family.

Data Structures
struct	clock_mchp_subsys_xosc_config
	External oscillator (XOSC) configuration. More...
struct	clock_mchp_subsys_dfll_config
	DFLL configuration. More...
struct	clock_mchp_subsys_fdpll_config
	Fractional DPLL (FDPLL) configuration. More...
struct	clock_mchp_subsys_rtc_config
	RTC clock configuration. More...
struct	clock_mchp_subsys_xosc32k_config
	32 kHz external oscillator (XOSC32K) configuration. More...
struct	clock_mchp_subsys_gclkgen_config
	GCLK generator configuration. More...
struct	clock_mchp_subsys_gclkperiph_config
	Peripheral GCLK channel configuration. More...
struct	clock_mchp_subsys_mclkcpu_config
	MCLK configuration structure. More...

Typedefs
typedef uint32_t *	clock_mchp_rate_t
	Clock rate datatype.

Enumerations
enum	clock_mchp_gclkgen {   CLOCK_MCHP_GCLKGEN_GEN0 , CLOCK_MCHP_GCLKGEN_GEN1 , CLOCK_MCHP_GCLKGEN_GEN2 , CLOCK_MCHP_GCLKGEN_GEN3 ,   CLOCK_MCHP_GCLKGEN_GEN4 , CLOCK_MCHP_GCLKGEN_GEN5 , CLOCK_MCHP_GCLKGEN_GEN6 , CLOCK_MCHP_GCLKGEN_GEN7 ,   CLOCK_MCHP_GCLKGEN_GEN8 , CLOCK_MCHP_GCLKGEN_GEN9 , CLOCK_MCHP_GCLKGEN_GEN10 , CLOCK_MCHP_GCLKGEN_GEN11 }
	GCLK generator numbers. More...
enum	clock_mchp_fdpll_src_clock {   CLOCK_MCHP_FDPLL_SRC_GCLK0 , CLOCK_MCHP_FDPLL_SRC_GCLK1 , CLOCK_MCHP_FDPLL_SRC_GCLK2 , CLOCK_MCHP_FDPLL_SRC_GCLK3 ,   CLOCK_MCHP_FDPLL_SRC_GCLK4 , CLOCK_MCHP_FDPLL_SRC_GCLK5 , CLOCK_MCHP_FDPLL_SRC_GCLK6 , CLOCK_MCHP_FDPLL_SRC_GCLK7 ,   CLOCK_MCHP_FDPLL_SRC_GCLK8 , CLOCK_MCHP_FDPLL_SRC_GCLK9 , CLOCK_MCHP_FDPLL_SRC_GCLK10 , CLOCK_MCHP_FDPLL_SRC_GCLK11 ,   CLOCK_MCHP_FDPLL_SRC_XOSC32K , CLOCK_MCHP_FDPLL_SRC_XOSC0 , CLOCK_MCHP_FDPLL_SRC_XOSC1 , CLOCK_MCHP_FDPLL_SRC_MAX = CLOCK_MCHP_FDPLL_SRC_XOSC1 }
	FDPLL source clocks. More...
enum	clock_mchp_rtc_src_clock { CLOCK_MCHP_RTC_SRC_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K , CLOCK_MCHP_RTC_SRC_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K , CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K , CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K }
	RTC source clocks. More...
enum	clock_mchp_gclk_src_clock {   CLOCK_MCHP_GCLK_SRC_XOSC0 , CLOCK_MCHP_GCLK_SRC_XOSC1 , CLOCK_MCHP_GCLK_SRC_GCLKPIN , CLOCK_MCHP_GCLK_SRC_GCLKGEN1 ,   CLOCK_MCHP_GCLK_SRC_OSCULP32K , CLOCK_MCHP_GCLK_SRC_XOSC32K , CLOCK_MCHP_GCLK_SRC_DFLL , CLOCK_MCHP_GCLK_SRC_FDPLL0 ,   CLOCK_MCHP_GCLK_SRC_FDPLL1 , CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_FDPLL1 }
	GCLK generator source clocks. More...
enum	clock_mchp_mclk_cpu_div {   CLOCK_MCHP_MCLK_CPU_DIV_1 = 1 , CLOCK_MCHP_MCLK_CPU_DIV_2 = 2 , CLOCK_MCHP_MCLK_CPU_DIV_4 = 4 , CLOCK_MCHP_MCLK_CPU_DIV_8 = 8 ,   CLOCK_MCHP_MCLK_CPU_DIV_16 = 16 , CLOCK_MCHP_MCLK_CPU_DIV_32 = 32 , CLOCK_MCHP_MCLK_CPU_DIV_64 = 64 , CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 }
	Division ratio of the MCLK prescaler for the CPU. More...

Detailed Description

Typedef Documentation

clock_mchp_rate_t

typedef uint32_t* clock_mchp_rate_t

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

Clock rate datatype.

Used for setting a clock rate.

Enumeration Type Documentation

clock_mchp_fdpll_src_clock

enum clock_mchp_fdpll_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

FDPLL source clocks.

Enumerator
CLOCK_MCHP_FDPLL_SRC_GCLK0	GCLK generator 0.
CLOCK_MCHP_FDPLL_SRC_GCLK1	GCLK generator 1.
CLOCK_MCHP_FDPLL_SRC_GCLK2	GCLK generator 2.
CLOCK_MCHP_FDPLL_SRC_GCLK3	GCLK generator 3.
CLOCK_MCHP_FDPLL_SRC_GCLK4	GCLK generator 4.
CLOCK_MCHP_FDPLL_SRC_GCLK5	GCLK generator 5.
CLOCK_MCHP_FDPLL_SRC_GCLK6	GCLK generator 6.
CLOCK_MCHP_FDPLL_SRC_GCLK7	GCLK generator 7.
CLOCK_MCHP_FDPLL_SRC_GCLK8	GCLK generator 8.
CLOCK_MCHP_FDPLL_SRC_GCLK9	GCLK generator 9.
CLOCK_MCHP_FDPLL_SRC_GCLK10	GCLK generator 10.
CLOCK_MCHP_FDPLL_SRC_GCLK11	GCLK generator 11.
CLOCK_MCHP_FDPLL_SRC_XOSC32K	32 kHz external oscillator.
CLOCK_MCHP_FDPLL_SRC_XOSC0	External oscillator 0.
CLOCK_MCHP_FDPLL_SRC_XOSC1	External oscillator 1.
CLOCK_MCHP_FDPLL_SRC_MAX	Highest valid source.

clock_mchp_gclk_src_clock

enum clock_mchp_gclk_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

GCLK generator source clocks.

Enumerator
CLOCK_MCHP_GCLK_SRC_XOSC0	External oscillator 0.
CLOCK_MCHP_GCLK_SRC_XOSC1	External oscillator 1.
CLOCK_MCHP_GCLK_SRC_GCLKPIN	GCLK input pin.
CLOCK_MCHP_GCLK_SRC_GCLKGEN1	GCLK generator 1.
CLOCK_MCHP_GCLK_SRC_OSCULP32K	Ultra-low-power 32 kHz oscillator.
CLOCK_MCHP_GCLK_SRC_XOSC32K	External 32 kHz oscillator.
CLOCK_MCHP_GCLK_SRC_DFLL	DFLL.
CLOCK_MCHP_GCLK_SRC_FDPLL0	Fractional DPLL 0.
CLOCK_MCHP_GCLK_SRC_FDPLL1	Fractional DPLL 1.
CLOCK_MCHP_GCLK_SRC_MAX	Highest valid source.

clock_mchp_gclkgen

enum clock_mchp_gclkgen

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

GCLK generator numbers.

Enumerator
CLOCK_MCHP_GCLKGEN_GEN0	Generator 0.
CLOCK_MCHP_GCLKGEN_GEN1	Generator 1.
CLOCK_MCHP_GCLKGEN_GEN2	Generator 2.
CLOCK_MCHP_GCLKGEN_GEN3	Generator 3.
CLOCK_MCHP_GCLKGEN_GEN4	Generator 4.
CLOCK_MCHP_GCLKGEN_GEN5	Generator 5.
CLOCK_MCHP_GCLKGEN_GEN6	Generator 6.
CLOCK_MCHP_GCLKGEN_GEN7	Generator 7.
CLOCK_MCHP_GCLKGEN_GEN8	Generator 8.
CLOCK_MCHP_GCLKGEN_GEN9	Generator 9.
CLOCK_MCHP_GCLKGEN_GEN10	Generator 10.
CLOCK_MCHP_GCLKGEN_GEN11	Generator 11.

clock_mchp_mclk_cpu_div

enum clock_mchp_mclk_cpu_div

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

Division ratio of the MCLK prescaler for the CPU.

Enumerator
CLOCK_MCHP_MCLK_CPU_DIV_1	Divide by 1.
CLOCK_MCHP_MCLK_CPU_DIV_2	Divide by 2.
CLOCK_MCHP_MCLK_CPU_DIV_4	Divide by 4.
CLOCK_MCHP_MCLK_CPU_DIV_8	Divide by 8.
CLOCK_MCHP_MCLK_CPU_DIV_16	Divide by 16.
CLOCK_MCHP_MCLK_CPU_DIV_32	Divide by 32.
CLOCK_MCHP_MCLK_CPU_DIV_64	Divide by 64.
CLOCK_MCHP_MCLK_CPU_DIV_128	Divide by 128.

clock_mchp_rtc_src_clock

enum clock_mchp_rtc_src_clock

#include <zephyr/drivers/clock_control/mchp_clock_sam_d5x_e5x.h>

RTC source clocks.

Enumerator
CLOCK_MCHP_RTC_SRC_ULP1K	Ultra-low-power 1 kHz.
CLOCK_MCHP_RTC_SRC_ULP32K	Ultra-low-power 32 kHz.
CLOCK_MCHP_RTC_SRC_XOSC1K	External 1 kHz.
CLOCK_MCHP_RTC_SRC_XOSC32K	External 32 kHz.