Zephyr API Documentation 4.4.99
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Peripheral Clocks (41-163)

Peripheral clock definitions based on MIMX9529 fsl_clock.h. More...

Macros

#define IMX952_CLK_ADC   (IMX952_CCM_NUM_CLK_SRC + 0)
 ADC clock.
#define IMX952_CLK_RESERVED1   (IMX952_CCM_NUM_CLK_SRC + 1)
 Reserved peripheral clock 1.
#define IMX952_CLK_BUSAON   (IMX952_CCM_NUM_CLK_SRC + 2)
 AON bus clock.
#define IMX952_CLK_CAN1   (IMX952_CCM_NUM_CLK_SRC + 3)
 CAN1 clock.
#define IMX952_CLK_RESERVED4   (IMX952_CCM_NUM_CLK_SRC + 4)
 Reserved peripheral clock 4.
#define IMX952_CLK_I3C1SLOW   (IMX952_CCM_NUM_CLK_SRC + 5)
 I3C1 slow clock.
#define IMX952_CLK_LPI2C1   (IMX952_CCM_NUM_CLK_SRC + 6)
 LPI2C1 clock.
#define IMX952_CLK_LPI2C2   (IMX952_CCM_NUM_CLK_SRC + 7)
 LPI2C2 clock.
#define IMX952_CLK_LPSPI1   (IMX952_CCM_NUM_CLK_SRC + 8)
 LPSPI1 clock.
#define IMX952_CLK_LPSPI2   (IMX952_CCM_NUM_CLK_SRC + 9)
 LPSPI2 clock.
#define IMX952_CLK_LPTMR1   (IMX952_CCM_NUM_CLK_SRC + 10)
 LPTMR1 clock.
#define IMX952_CLK_LPUART1   (IMX952_CCM_NUM_CLK_SRC + 11)
 LPUART1 clock.
#define IMX952_CLK_LPUART2   (IMX952_CCM_NUM_CLK_SRC + 12)
 LPUART2 clock.
#define IMX952_CLK_M33   (IMX952_CCM_NUM_CLK_SRC + 13)
 Cortex-M33 core clock.
#define IMX952_CLK_M33SYSTICK   (IMX952_CCM_NUM_CLK_SRC + 14)
 Cortex-M33 SysTick clock.
#define IMX952_CLK_RESERVED15   (IMX952_CCM_NUM_CLK_SRC + 15)
 Reserved peripheral clock 15.
#define IMX952_CLK_PDM   (IMX952_CCM_NUM_CLK_SRC + 16)
 PDM clock.
#define IMX952_CLK_SAI1   (IMX952_CCM_NUM_CLK_SRC + 17)
 SAI1 clock.
#define IMX952_CLK_RESERVED18   (IMX952_CCM_NUM_CLK_SRC + 18)
 Reserved peripheral clock 18.
#define IMX952_CLK_TPM2   (IMX952_CCM_NUM_CLK_SRC + 19)
 TPM2 clock.
#define IMX952_CLK_RESERVED20   (IMX952_CCM_NUM_CLK_SRC + 20)
 Reserved peripheral clock 20.
#define IMX952_CLK_CAMAPB   (IMX952_CCM_NUM_CLK_SRC + 21)
 Camera APB clock.
#define IMX952_CLK_CAMAXI   (IMX952_CCM_NUM_CLK_SRC + 22)
 Camera AXI clock.
#define IMX952_CLK_CAMCM0   (IMX952_CCM_NUM_CLK_SRC + 23)
 Camera CM0 clock.
#define IMX952_CLK_CAMISI   (IMX952_CCM_NUM_CLK_SRC + 24)
 Camera ISI clock.
#define IMX952_CLK_CAMPHYCFG   (IMX952_CCM_NUM_CLK_SRC + 25)
 Camera PHY configuration clock.
#define IMX952_CLK_MIPIPHYPLLBYPASS   (IMX952_CCM_NUM_CLK_SRC + 26)
 MIPI PHY PLL bypass clock.
#define IMX952_CLK_RESERVED27   (IMX952_CCM_NUM_CLK_SRC + 27)
 Reserved peripheral clock 27.
#define IMX952_CLK_MIPITESTBYTE   (IMX952_CCM_NUM_CLK_SRC + 28)
 MIPI test byte clock.
#define IMX952_CLK_A55   (IMX952_CCM_NUM_CLK_SRC + 29)
 Cortex-A55 core clock.
#define IMX952_CLK_A55MTRBUS   (IMX952_CCM_NUM_CLK_SRC + 30)
 Cortex-A55 MTR bus clock.
#define IMX952_CLK_A55PERIPH   (IMX952_CCM_NUM_CLK_SRC + 31)
 Cortex-A55 peripheral clock.
#define IMX952_CLK_DRAMALT   (IMX952_CCM_NUM_CLK_SRC + 32)
 DRAM alternate clock.
#define IMX952_CLK_DRAMAPB   (IMX952_CCM_NUM_CLK_SRC + 33)
 DRAM APB clock.
#define IMX952_CLK_DISPAPB   (IMX952_CCM_NUM_CLK_SRC + 34)
 Display APB clock.
#define IMX952_CLK_DISPAXI   (IMX952_CCM_NUM_CLK_SRC + 35)
 Display AXI clock.
#define IMX952_CLK_DISPLPSPI   (IMX952_CCM_NUM_CLK_SRC + 36)
 Display LPSPI clock.
#define IMX952_CLK_DISPOCRAM   (IMX952_CCM_NUM_CLK_SRC + 37)
 Display OCRAM clock.
#define IMX952_CLK_DISPHYCFG   (IMX952_CCM_NUM_CLK_SRC + 38)
 Display PHY configuration clock.
#define IMX952_CLK_DISP1PIX   (IMX952_CCM_NUM_CLK_SRC + 39)
 Display 1 pixel clock.
#define IMX952_CLK_DISPCDPHYAPB   (IMX952_CCM_NUM_CLK_SRC + 40)
 Display CD PHY APB clock.
#define IMX952_CLK_RESERVED41   (IMX952_CCM_NUM_CLK_SRC + 41)
 Reserved peripheral clock 41.
#define IMX952_CLK_GPUAPB   (IMX952_CCM_NUM_CLK_SRC + 42)
 GPU APB clock.
#define IMX952_CLK_GPU   (IMX952_CCM_NUM_CLK_SRC + 43)
 GPU core clock.
#define IMX952_CLK_HSIOACSCAN480M   (IMX952_CCM_NUM_CLK_SRC + 44)
 HSIO AC scan 480MHz clock.
#define IMX952_CLK_HSIOACSCAN80M   (IMX952_CCM_NUM_CLK_SRC + 45)
 HSIO AC scan 80MHz clock.
#define IMX952_CLK_HSIO   (IMX952_CCM_NUM_CLK_SRC + 46)
 HSIO bus clock.
#define IMX952_CLK_HSIOPCIEAUX   (IMX952_CCM_NUM_CLK_SRC + 47)
 HSIO PCIe auxiliary clock.
#define IMX952_CLK_HSIOPCIETEST160M   (IMX952_CCM_NUM_CLK_SRC + 48)
 HSIO PCIe test 160MHz clock.
#define IMX952_CLK_HSIOPCIETEST400M   (IMX952_CCM_NUM_CLK_SRC + 49)
 HSIO PCIe test 400MHz clock.
#define IMX952_CLK_HSIOPCIETEST500M   (IMX952_CCM_NUM_CLK_SRC + 50)
 HSIO PCIe test 500MHz clock.
#define IMX952_CLK_HSIOUSBTEST50M   (IMX952_CCM_NUM_CLK_SRC + 51)
 HSIO USB test 50MHz clock.
#define IMX952_CLK_HSIOUSBTEST60M   (IMX952_CCM_NUM_CLK_SRC + 52)
 HSIO USB test 60MHz clock.
#define IMX952_CLK_BUSM7   (IMX952_CCM_NUM_CLK_SRC + 53)
 M7 bus clock.
#define IMX952_CLK_M7   (IMX952_CCM_NUM_CLK_SRC + 54)
 Cortex-M7 core clock.
#define IMX952_CLK_M7SYSTICK   (IMX952_CCM_NUM_CLK_SRC + 55)
 Cortex-M7 SysTick clock.
#define IMX952_CLK_BUSNETCMIX   (IMX952_CCM_NUM_CLK_SRC + 56)
 Network mix bus clock.
#define IMX952_CLK_ENET   (IMX952_CCM_NUM_CLK_SRC + 57)
 Ethernet clock.
#define IMX952_CLK_ENETPHYTEST200M   (IMX952_CCM_NUM_CLK_SRC + 58)
 Ethernet PHY test 200MHz clock.
#define IMX952_CLK_ENETPHYTEST500M   (IMX952_CCM_NUM_CLK_SRC + 59)
 Ethernet PHY test 500MHz clock.
#define IMX952_CLK_ENETPHYTEST667M   (IMX952_CCM_NUM_CLK_SRC + 60)
 Ethernet PHY test 667MHz clock.
#define IMX952_CLK_ENETREF   (IMX952_CCM_NUM_CLK_SRC + 61)
 Ethernet reference clock.
#define IMX952_CLK_ENETTIMER1   (IMX952_CCM_NUM_CLK_SRC + 62)
 Ethernet timer 1 clock.
#define IMX952_CLK_RESERVED63   (IMX952_CCM_NUM_CLK_SRC + 63)
 Reserved peripheral clock 63.
#define IMX952_CLK_SAI2   (IMX952_CCM_NUM_CLK_SRC + 64)
 SAI2 clock.
#define IMX952_CLK_NOCAPB   (IMX952_CCM_NUM_CLK_SRC + 65)
 NOC APB clock.
#define IMX952_CLK_NOC   (IMX952_CCM_NUM_CLK_SRC + 66)
 Network-on-chip clock.
#define IMX952_CLK_NPUAPB   (IMX952_CCM_NUM_CLK_SRC + 67)
 NPU APB clock.
#define IMX952_CLK_NPU   (IMX952_CCM_NUM_CLK_SRC + 68)
 Neural processing unit clock.
#define IMX952_CLK_CCMCKO1   (IMX952_CCM_NUM_CLK_SRC + 69)
 CCM clock output 1.
#define IMX952_CLK_CCMCKO2   (IMX952_CCM_NUM_CLK_SRC + 70)
 CCM clock output 2.
#define IMX952_CLK_CCMCKO3   (IMX952_CCM_NUM_CLK_SRC + 71)
 CCM clock output 3.
#define IMX952_CLK_CCMCKO4   (IMX952_CCM_NUM_CLK_SRC + 72)
 CCM clock output 4.
#define IMX952_CLK_VPUAPB   (IMX952_CCM_NUM_CLK_SRC + 73)
 VPU APB clock.
#define IMX952_CLK_VPU   (IMX952_CCM_NUM_CLK_SRC + 74)
 Video processing unit clock.
#define IMX952_CLK_RESERVED75   (IMX952_CCM_NUM_CLK_SRC + 75)
 Reserved peripheral clock 75.
#define IMX952_CLK_RESERVED76   (IMX952_CCM_NUM_CLK_SRC + 76)
 Reserved peripheral clock 76.
#define IMX952_CLK_AUDIOXCVR   (IMX952_CCM_NUM_CLK_SRC + 77)
 Audio transceiver clock.
#define IMX952_CLK_BUSWAKEUP   (IMX952_CCM_NUM_CLK_SRC + 78)
 Wakeup bus clock.
#define IMX952_CLK_CAN2   (IMX952_CCM_NUM_CLK_SRC + 79)
 CAN2 clock.
#define IMX952_CLK_CAN3   (IMX952_CCM_NUM_CLK_SRC + 80)
 CAN3 clock.
#define IMX952_CLK_CAN4   (IMX952_CCM_NUM_CLK_SRC + 81)
 CAN4 clock.
#define IMX952_CLK_CAN5   (IMX952_CCM_NUM_CLK_SRC + 82)
 CAN5 clock.
#define IMX952_CLK_FLEXIO1   (IMX952_CCM_NUM_CLK_SRC + 83)
 FlexIO1 clock.
#define IMX952_CLK_FLEXIO2   (IMX952_CCM_NUM_CLK_SRC + 84)
 FlexIO2 clock.
#define IMX952_CLK_XSPI1   (IMX952_CCM_NUM_CLK_SRC + 85)
 eXecute-in-place SPI 1 clock
#define IMX952_CLK_RESERVED86   (IMX952_CCM_NUM_CLK_SRC + 86)
 Reserved peripheral clock 86.
#define IMX952_CLK_I3C2SLOW   (IMX952_CCM_NUM_CLK_SRC + 87)
 I3C2 slow clock.
#define IMX952_CLK_LPI2C3   (IMX952_CCM_NUM_CLK_SRC + 88)
 LPI2C3 clock.
#define IMX952_CLK_LPI2C4   (IMX952_CCM_NUM_CLK_SRC + 89)
 LPI2C4 clock.
#define IMX952_CLK_LPI2C5   (IMX952_CCM_NUM_CLK_SRC + 90)
 LPI2C5 clock.
#define IMX952_CLK_LPI2C6   (IMX952_CCM_NUM_CLK_SRC + 91)
 LPI2C6 clock.
#define IMX952_CLK_LPI2C7   (IMX952_CCM_NUM_CLK_SRC + 92)
 LPI2C7 clock.
#define IMX952_CLK_LPI2C8   (IMX952_CCM_NUM_CLK_SRC + 93)
 LPI2C8 clock.
#define IMX952_CLK_LPSPI3   (IMX952_CCM_NUM_CLK_SRC + 94)
 LPSPI3 clock.
#define IMX952_CLK_LPSPI4   (IMX952_CCM_NUM_CLK_SRC + 95)
 LPSPI4 clock.
#define IMX952_CLK_LPSPI5   (IMX952_CCM_NUM_CLK_SRC + 96)
 LPSPI5 clock.
#define IMX952_CLK_LPSPI6   (IMX952_CCM_NUM_CLK_SRC + 97)
 LPSPI6 clock.
#define IMX952_CLK_LPSPI7   (IMX952_CCM_NUM_CLK_SRC + 98)
 LPSPI7 clock.
#define IMX952_CLK_LPSPI8   (IMX952_CCM_NUM_CLK_SRC + 99)
 LPSPI8 clock.
#define IMX952_CLK_LPTMR2   (IMX952_CCM_NUM_CLK_SRC + 100)
 LPTMR2 clock.
#define IMX952_CLK_LPUART3   (IMX952_CCM_NUM_CLK_SRC + 101)
 LPUART3 clock.
#define IMX952_CLK_LPUART4   (IMX952_CCM_NUM_CLK_SRC + 102)
 LPUART4 clock.
#define IMX952_CLK_LPUART5   (IMX952_CCM_NUM_CLK_SRC + 103)
 LPUART5 clock.
#define IMX952_CLK_LPUART6   (IMX952_CCM_NUM_CLK_SRC + 104)
 LPUART6 clock.
#define IMX952_CLK_LPUART7   (IMX952_CCM_NUM_CLK_SRC + 105)
 LPUART7 clock.
#define IMX952_CLK_LPUART8   (IMX952_CCM_NUM_CLK_SRC + 106)
 LPUART8 clock.
#define IMX952_CLK_SAI3   (IMX952_CCM_NUM_CLK_SRC + 107)
 SAI3 clock.
#define IMX952_CLK_SAI4   (IMX952_CCM_NUM_CLK_SRC + 108)
 SAI4 clock.
#define IMX952_CLK_SAI5   (IMX952_CCM_NUM_CLK_SRC + 109)
 SAI5 clock.
#define IMX952_CLK_SPDIF   (IMX952_CCM_NUM_CLK_SRC + 110)
 S/PDIF clock.
#define IMX952_CLK_SWOTRACE   (IMX952_CCM_NUM_CLK_SRC + 111)
 SWO trace clock.
#define IMX952_CLK_TPM4   (IMX952_CCM_NUM_CLK_SRC + 112)
 TPM4 clock.
#define IMX952_CLK_TPM5   (IMX952_CCM_NUM_CLK_SRC + 113)
 TPM5 clock.
#define IMX952_CLK_TPM6   (IMX952_CCM_NUM_CLK_SRC + 114)
 TPM6 clock.
#define IMX952_CLK_TSTMR2   (IMX952_CCM_NUM_CLK_SRC + 115)
 Timestamp timer 2 clock.
#define IMX952_CLK_USBPHYBURUNIN   (IMX952_CCM_NUM_CLK_SRC + 116)
 USB PHY burn-in clock.
#define IMX952_CLK_USDHC1   (IMX952_CCM_NUM_CLK_SRC + 117)
 uSDHC1 clock
#define IMX952_CLK_USDHC2   (IMX952_CCM_NUM_CLK_SRC + 118)
 uSDHC2 clock
#define IMX952_CLK_USDHC3   (IMX952_CCM_NUM_CLK_SRC + 119)
 uSDHC3 clock
#define IMX952_CLK_V2XPK   (IMX952_CCM_NUM_CLK_SRC + 120)
 V2X packet engine clock.
#define IMX952_CLK_WAKEUPAXI   (IMX952_CCM_NUM_CLK_SRC + 121)
 Wakeup AXI clock.
#define IMX952_CLK_XSPISLVROOT   (IMX952_CCM_NUM_CLK_SRC + 122)
 XPI slave root clock.
#define IMX952_CLK_AUDMIX1   (IMX952_CCM_NUM_CLK_SRC + 123)
 Audio Mixer 1 clock.
#define IMX952_CLK_ASRC1   (IMX952_CCM_NUM_CLK_SRC + 124)
 Asynchronous Sample Rate Converter 1 clock.
#define IMX952_CLK_ASRC2   (IMX952_CCM_NUM_CLK_SRC + 125)
 Asynchronous Sample Rate Converter 2 clock.
#define IMX952_CLK_GPT2   (IMX952_CCM_NUM_CLK_SRC + 126)
 General Purpose Timer 2 clock.
#define IMX952_CLK_GPT3   (IMX952_CCM_NUM_CLK_SRC + 127)
 General Purpose Timer 3 clock.
#define IMX952_CLK_GPT4   (IMX952_CCM_NUM_CLK_SRC + 128)
 General Purpose Timer 4 clock.
#define IMX952_CLK_GPT5   (IMX952_CCM_NUM_CLK_SRC + 129)
 General Purpose Timer 5 clock.

Detailed Description

Peripheral clock definitions based on MIMX9529 fsl_clock.h.

Macro Definition Documentation

◆ IMX952_CLK_A55

#define IMX952_CLK_A55   (IMX952_CCM_NUM_CLK_SRC + 29)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-A55 core clock.

◆ IMX952_CLK_A55MTRBUS

#define IMX952_CLK_A55MTRBUS   (IMX952_CCM_NUM_CLK_SRC + 30)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-A55 MTR bus clock.

◆ IMX952_CLK_A55PERIPH

#define IMX952_CLK_A55PERIPH   (IMX952_CCM_NUM_CLK_SRC + 31)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-A55 peripheral clock.

◆ IMX952_CLK_ADC

#define IMX952_CLK_ADC   (IMX952_CCM_NUM_CLK_SRC + 0)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

ADC clock.

◆ IMX952_CLK_ASRC1

#define IMX952_CLK_ASRC1   (IMX952_CCM_NUM_CLK_SRC + 124)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Asynchronous Sample Rate Converter 1 clock.

◆ IMX952_CLK_ASRC2

#define IMX952_CLK_ASRC2   (IMX952_CCM_NUM_CLK_SRC + 125)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Asynchronous Sample Rate Converter 2 clock.

◆ IMX952_CLK_AUDIOXCVR

#define IMX952_CLK_AUDIOXCVR   (IMX952_CCM_NUM_CLK_SRC + 77)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Audio transceiver clock.

◆ IMX952_CLK_AUDMIX1

#define IMX952_CLK_AUDMIX1   (IMX952_CCM_NUM_CLK_SRC + 123)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Audio Mixer 1 clock.

◆ IMX952_CLK_BUSAON

#define IMX952_CLK_BUSAON   (IMX952_CCM_NUM_CLK_SRC + 2)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

AON bus clock.

◆ IMX952_CLK_BUSM7

#define IMX952_CLK_BUSM7   (IMX952_CCM_NUM_CLK_SRC + 53)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

M7 bus clock.

◆ IMX952_CLK_BUSNETCMIX

#define IMX952_CLK_BUSNETCMIX   (IMX952_CCM_NUM_CLK_SRC + 56)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Network mix bus clock.

◆ IMX952_CLK_BUSWAKEUP

#define IMX952_CLK_BUSWAKEUP   (IMX952_CCM_NUM_CLK_SRC + 78)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Wakeup bus clock.

◆ IMX952_CLK_CAMAPB

#define IMX952_CLK_CAMAPB   (IMX952_CCM_NUM_CLK_SRC + 21)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Camera APB clock.

◆ IMX952_CLK_CAMAXI

#define IMX952_CLK_CAMAXI   (IMX952_CCM_NUM_CLK_SRC + 22)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Camera AXI clock.

◆ IMX952_CLK_CAMCM0

#define IMX952_CLK_CAMCM0   (IMX952_CCM_NUM_CLK_SRC + 23)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Camera CM0 clock.

◆ IMX952_CLK_CAMISI

#define IMX952_CLK_CAMISI   (IMX952_CCM_NUM_CLK_SRC + 24)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Camera ISI clock.

◆ IMX952_CLK_CAMPHYCFG

#define IMX952_CLK_CAMPHYCFG   (IMX952_CCM_NUM_CLK_SRC + 25)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Camera PHY configuration clock.

◆ IMX952_CLK_CAN1

#define IMX952_CLK_CAN1   (IMX952_CCM_NUM_CLK_SRC + 3)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CAN1 clock.

◆ IMX952_CLK_CAN2

#define IMX952_CLK_CAN2   (IMX952_CCM_NUM_CLK_SRC + 79)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CAN2 clock.

◆ IMX952_CLK_CAN3

#define IMX952_CLK_CAN3   (IMX952_CCM_NUM_CLK_SRC + 80)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CAN3 clock.

◆ IMX952_CLK_CAN4

#define IMX952_CLK_CAN4   (IMX952_CCM_NUM_CLK_SRC + 81)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CAN4 clock.

◆ IMX952_CLK_CAN5

#define IMX952_CLK_CAN5   (IMX952_CCM_NUM_CLK_SRC + 82)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CAN5 clock.

◆ IMX952_CLK_CCMCKO1

#define IMX952_CLK_CCMCKO1   (IMX952_CCM_NUM_CLK_SRC + 69)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CCM clock output 1.

◆ IMX952_CLK_CCMCKO2

#define IMX952_CLK_CCMCKO2   (IMX952_CCM_NUM_CLK_SRC + 70)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CCM clock output 2.

◆ IMX952_CLK_CCMCKO3

#define IMX952_CLK_CCMCKO3   (IMX952_CCM_NUM_CLK_SRC + 71)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CCM clock output 3.

◆ IMX952_CLK_CCMCKO4

#define IMX952_CLK_CCMCKO4   (IMX952_CCM_NUM_CLK_SRC + 72)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

CCM clock output 4.

◆ IMX952_CLK_DISP1PIX

#define IMX952_CLK_DISP1PIX   (IMX952_CCM_NUM_CLK_SRC + 39)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display 1 pixel clock.

◆ IMX952_CLK_DISPAPB

#define IMX952_CLK_DISPAPB   (IMX952_CCM_NUM_CLK_SRC + 34)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display APB clock.

◆ IMX952_CLK_DISPAXI

#define IMX952_CLK_DISPAXI   (IMX952_CCM_NUM_CLK_SRC + 35)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display AXI clock.

◆ IMX952_CLK_DISPCDPHYAPB

#define IMX952_CLK_DISPCDPHYAPB   (IMX952_CCM_NUM_CLK_SRC + 40)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display CD PHY APB clock.

◆ IMX952_CLK_DISPHYCFG

#define IMX952_CLK_DISPHYCFG   (IMX952_CCM_NUM_CLK_SRC + 38)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display PHY configuration clock.

◆ IMX952_CLK_DISPLPSPI

#define IMX952_CLK_DISPLPSPI   (IMX952_CCM_NUM_CLK_SRC + 36)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display LPSPI clock.

◆ IMX952_CLK_DISPOCRAM

#define IMX952_CLK_DISPOCRAM   (IMX952_CCM_NUM_CLK_SRC + 37)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Display OCRAM clock.

◆ IMX952_CLK_DRAMALT

#define IMX952_CLK_DRAMALT   (IMX952_CCM_NUM_CLK_SRC + 32)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

DRAM alternate clock.

◆ IMX952_CLK_DRAMAPB

#define IMX952_CLK_DRAMAPB   (IMX952_CCM_NUM_CLK_SRC + 33)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

DRAM APB clock.

◆ IMX952_CLK_ENET

#define IMX952_CLK_ENET   (IMX952_CCM_NUM_CLK_SRC + 57)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet clock.

◆ IMX952_CLK_ENETPHYTEST200M

#define IMX952_CLK_ENETPHYTEST200M   (IMX952_CCM_NUM_CLK_SRC + 58)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet PHY test 200MHz clock.

◆ IMX952_CLK_ENETPHYTEST500M

#define IMX952_CLK_ENETPHYTEST500M   (IMX952_CCM_NUM_CLK_SRC + 59)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet PHY test 500MHz clock.

◆ IMX952_CLK_ENETPHYTEST667M

#define IMX952_CLK_ENETPHYTEST667M   (IMX952_CCM_NUM_CLK_SRC + 60)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet PHY test 667MHz clock.

◆ IMX952_CLK_ENETREF

#define IMX952_CLK_ENETREF   (IMX952_CCM_NUM_CLK_SRC + 61)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet reference clock.

◆ IMX952_CLK_ENETTIMER1

#define IMX952_CLK_ENETTIMER1   (IMX952_CCM_NUM_CLK_SRC + 62)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Ethernet timer 1 clock.

◆ IMX952_CLK_FLEXIO1

#define IMX952_CLK_FLEXIO1   (IMX952_CCM_NUM_CLK_SRC + 83)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

FlexIO1 clock.

◆ IMX952_CLK_FLEXIO2

#define IMX952_CLK_FLEXIO2   (IMX952_CCM_NUM_CLK_SRC + 84)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

FlexIO2 clock.

◆ IMX952_CLK_GPT2

#define IMX952_CLK_GPT2   (IMX952_CCM_NUM_CLK_SRC + 126)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

General Purpose Timer 2 clock.

◆ IMX952_CLK_GPT3

#define IMX952_CLK_GPT3   (IMX952_CCM_NUM_CLK_SRC + 127)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

General Purpose Timer 3 clock.

◆ IMX952_CLK_GPT4

#define IMX952_CLK_GPT4   (IMX952_CCM_NUM_CLK_SRC + 128)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

General Purpose Timer 4 clock.

◆ IMX952_CLK_GPT5

#define IMX952_CLK_GPT5   (IMX952_CCM_NUM_CLK_SRC + 129)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

General Purpose Timer 5 clock.

◆ IMX952_CLK_GPU

#define IMX952_CLK_GPU   (IMX952_CCM_NUM_CLK_SRC + 43)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

GPU core clock.

◆ IMX952_CLK_GPUAPB

#define IMX952_CLK_GPUAPB   (IMX952_CCM_NUM_CLK_SRC + 42)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

GPU APB clock.

◆ IMX952_CLK_HSIO

#define IMX952_CLK_HSIO   (IMX952_CCM_NUM_CLK_SRC + 46)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO bus clock.

◆ IMX952_CLK_HSIOACSCAN480M

#define IMX952_CLK_HSIOACSCAN480M   (IMX952_CCM_NUM_CLK_SRC + 44)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO AC scan 480MHz clock.

◆ IMX952_CLK_HSIOACSCAN80M

#define IMX952_CLK_HSIOACSCAN80M   (IMX952_CCM_NUM_CLK_SRC + 45)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO AC scan 80MHz clock.

◆ IMX952_CLK_HSIOPCIEAUX

#define IMX952_CLK_HSIOPCIEAUX   (IMX952_CCM_NUM_CLK_SRC + 47)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO PCIe auxiliary clock.

◆ IMX952_CLK_HSIOPCIETEST160M

#define IMX952_CLK_HSIOPCIETEST160M   (IMX952_CCM_NUM_CLK_SRC + 48)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO PCIe test 160MHz clock.

◆ IMX952_CLK_HSIOPCIETEST400M

#define IMX952_CLK_HSIOPCIETEST400M   (IMX952_CCM_NUM_CLK_SRC + 49)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO PCIe test 400MHz clock.

◆ IMX952_CLK_HSIOPCIETEST500M

#define IMX952_CLK_HSIOPCIETEST500M   (IMX952_CCM_NUM_CLK_SRC + 50)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO PCIe test 500MHz clock.

◆ IMX952_CLK_HSIOUSBTEST50M

#define IMX952_CLK_HSIOUSBTEST50M   (IMX952_CCM_NUM_CLK_SRC + 51)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO USB test 50MHz clock.

◆ IMX952_CLK_HSIOUSBTEST60M

#define IMX952_CLK_HSIOUSBTEST60M   (IMX952_CCM_NUM_CLK_SRC + 52)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

HSIO USB test 60MHz clock.

◆ IMX952_CLK_I3C1SLOW

#define IMX952_CLK_I3C1SLOW   (IMX952_CCM_NUM_CLK_SRC + 5)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

I3C1 slow clock.

◆ IMX952_CLK_I3C2SLOW

#define IMX952_CLK_I3C2SLOW   (IMX952_CCM_NUM_CLK_SRC + 87)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

I3C2 slow clock.

◆ IMX952_CLK_LPI2C1

#define IMX952_CLK_LPI2C1   (IMX952_CCM_NUM_CLK_SRC + 6)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C1 clock.

◆ IMX952_CLK_LPI2C2

#define IMX952_CLK_LPI2C2   (IMX952_CCM_NUM_CLK_SRC + 7)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C2 clock.

◆ IMX952_CLK_LPI2C3

#define IMX952_CLK_LPI2C3   (IMX952_CCM_NUM_CLK_SRC + 88)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C3 clock.

◆ IMX952_CLK_LPI2C4

#define IMX952_CLK_LPI2C4   (IMX952_CCM_NUM_CLK_SRC + 89)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C4 clock.

◆ IMX952_CLK_LPI2C5

#define IMX952_CLK_LPI2C5   (IMX952_CCM_NUM_CLK_SRC + 90)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C5 clock.

◆ IMX952_CLK_LPI2C6

#define IMX952_CLK_LPI2C6   (IMX952_CCM_NUM_CLK_SRC + 91)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C6 clock.

◆ IMX952_CLK_LPI2C7

#define IMX952_CLK_LPI2C7   (IMX952_CCM_NUM_CLK_SRC + 92)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C7 clock.

◆ IMX952_CLK_LPI2C8

#define IMX952_CLK_LPI2C8   (IMX952_CCM_NUM_CLK_SRC + 93)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPI2C8 clock.

◆ IMX952_CLK_LPSPI1

#define IMX952_CLK_LPSPI1   (IMX952_CCM_NUM_CLK_SRC + 8)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI1 clock.

◆ IMX952_CLK_LPSPI2

#define IMX952_CLK_LPSPI2   (IMX952_CCM_NUM_CLK_SRC + 9)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI2 clock.

◆ IMX952_CLK_LPSPI3

#define IMX952_CLK_LPSPI3   (IMX952_CCM_NUM_CLK_SRC + 94)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI3 clock.

◆ IMX952_CLK_LPSPI4

#define IMX952_CLK_LPSPI4   (IMX952_CCM_NUM_CLK_SRC + 95)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI4 clock.

◆ IMX952_CLK_LPSPI5

#define IMX952_CLK_LPSPI5   (IMX952_CCM_NUM_CLK_SRC + 96)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI5 clock.

◆ IMX952_CLK_LPSPI6

#define IMX952_CLK_LPSPI6   (IMX952_CCM_NUM_CLK_SRC + 97)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI6 clock.

◆ IMX952_CLK_LPSPI7

#define IMX952_CLK_LPSPI7   (IMX952_CCM_NUM_CLK_SRC + 98)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI7 clock.

◆ IMX952_CLK_LPSPI8

#define IMX952_CLK_LPSPI8   (IMX952_CCM_NUM_CLK_SRC + 99)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPSPI8 clock.

◆ IMX952_CLK_LPTMR1

#define IMX952_CLK_LPTMR1   (IMX952_CCM_NUM_CLK_SRC + 10)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPTMR1 clock.

◆ IMX952_CLK_LPTMR2

#define IMX952_CLK_LPTMR2   (IMX952_CCM_NUM_CLK_SRC + 100)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPTMR2 clock.

◆ IMX952_CLK_LPUART1

#define IMX952_CLK_LPUART1   (IMX952_CCM_NUM_CLK_SRC + 11)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART1 clock.

◆ IMX952_CLK_LPUART2

#define IMX952_CLK_LPUART2   (IMX952_CCM_NUM_CLK_SRC + 12)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART2 clock.

◆ IMX952_CLK_LPUART3

#define IMX952_CLK_LPUART3   (IMX952_CCM_NUM_CLK_SRC + 101)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART3 clock.

◆ IMX952_CLK_LPUART4

#define IMX952_CLK_LPUART4   (IMX952_CCM_NUM_CLK_SRC + 102)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART4 clock.

◆ IMX952_CLK_LPUART5

#define IMX952_CLK_LPUART5   (IMX952_CCM_NUM_CLK_SRC + 103)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART5 clock.

◆ IMX952_CLK_LPUART6

#define IMX952_CLK_LPUART6   (IMX952_CCM_NUM_CLK_SRC + 104)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART6 clock.

◆ IMX952_CLK_LPUART7

#define IMX952_CLK_LPUART7   (IMX952_CCM_NUM_CLK_SRC + 105)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART7 clock.

◆ IMX952_CLK_LPUART8

#define IMX952_CLK_LPUART8   (IMX952_CCM_NUM_CLK_SRC + 106)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

LPUART8 clock.

◆ IMX952_CLK_M33

#define IMX952_CLK_M33   (IMX952_CCM_NUM_CLK_SRC + 13)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-M33 core clock.

◆ IMX952_CLK_M33SYSTICK

#define IMX952_CLK_M33SYSTICK   (IMX952_CCM_NUM_CLK_SRC + 14)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-M33 SysTick clock.

◆ IMX952_CLK_M7

#define IMX952_CLK_M7   (IMX952_CCM_NUM_CLK_SRC + 54)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-M7 core clock.

◆ IMX952_CLK_M7SYSTICK

#define IMX952_CLK_M7SYSTICK   (IMX952_CCM_NUM_CLK_SRC + 55)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Cortex-M7 SysTick clock.

◆ IMX952_CLK_MIPIPHYPLLBYPASS

#define IMX952_CLK_MIPIPHYPLLBYPASS   (IMX952_CCM_NUM_CLK_SRC + 26)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

MIPI PHY PLL bypass clock.

◆ IMX952_CLK_MIPITESTBYTE

#define IMX952_CLK_MIPITESTBYTE   (IMX952_CCM_NUM_CLK_SRC + 28)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

MIPI test byte clock.

◆ IMX952_CLK_NOC

#define IMX952_CLK_NOC   (IMX952_CCM_NUM_CLK_SRC + 66)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Network-on-chip clock.

◆ IMX952_CLK_NOCAPB

#define IMX952_CLK_NOCAPB   (IMX952_CCM_NUM_CLK_SRC + 65)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

NOC APB clock.

◆ IMX952_CLK_NPU

#define IMX952_CLK_NPU   (IMX952_CCM_NUM_CLK_SRC + 68)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Neural processing unit clock.

◆ IMX952_CLK_NPUAPB

#define IMX952_CLK_NPUAPB   (IMX952_CCM_NUM_CLK_SRC + 67)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

NPU APB clock.

◆ IMX952_CLK_PDM

#define IMX952_CLK_PDM   (IMX952_CCM_NUM_CLK_SRC + 16)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

PDM clock.

◆ IMX952_CLK_RESERVED1

#define IMX952_CLK_RESERVED1   (IMX952_CCM_NUM_CLK_SRC + 1)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 1.

◆ IMX952_CLK_RESERVED15

#define IMX952_CLK_RESERVED15   (IMX952_CCM_NUM_CLK_SRC + 15)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 15.

◆ IMX952_CLK_RESERVED18

#define IMX952_CLK_RESERVED18   (IMX952_CCM_NUM_CLK_SRC + 18)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 18.

◆ IMX952_CLK_RESERVED20

#define IMX952_CLK_RESERVED20   (IMX952_CCM_NUM_CLK_SRC + 20)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 20.

◆ IMX952_CLK_RESERVED27

#define IMX952_CLK_RESERVED27   (IMX952_CCM_NUM_CLK_SRC + 27)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 27.

◆ IMX952_CLK_RESERVED4

#define IMX952_CLK_RESERVED4   (IMX952_CCM_NUM_CLK_SRC + 4)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 4.

◆ IMX952_CLK_RESERVED41

#define IMX952_CLK_RESERVED41   (IMX952_CCM_NUM_CLK_SRC + 41)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 41.

◆ IMX952_CLK_RESERVED63

#define IMX952_CLK_RESERVED63   (IMX952_CCM_NUM_CLK_SRC + 63)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 63.

◆ IMX952_CLK_RESERVED75

#define IMX952_CLK_RESERVED75   (IMX952_CCM_NUM_CLK_SRC + 75)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 75.

◆ IMX952_CLK_RESERVED76

#define IMX952_CLK_RESERVED76   (IMX952_CCM_NUM_CLK_SRC + 76)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 76.

◆ IMX952_CLK_RESERVED86

#define IMX952_CLK_RESERVED86   (IMX952_CCM_NUM_CLK_SRC + 86)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Reserved peripheral clock 86.

◆ IMX952_CLK_SAI1

#define IMX952_CLK_SAI1   (IMX952_CCM_NUM_CLK_SRC + 17)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SAI1 clock.

◆ IMX952_CLK_SAI2

#define IMX952_CLK_SAI2   (IMX952_CCM_NUM_CLK_SRC + 64)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SAI2 clock.

◆ IMX952_CLK_SAI3

#define IMX952_CLK_SAI3   (IMX952_CCM_NUM_CLK_SRC + 107)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SAI3 clock.

◆ IMX952_CLK_SAI4

#define IMX952_CLK_SAI4   (IMX952_CCM_NUM_CLK_SRC + 108)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SAI4 clock.

◆ IMX952_CLK_SAI5

#define IMX952_CLK_SAI5   (IMX952_CCM_NUM_CLK_SRC + 109)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SAI5 clock.

◆ IMX952_CLK_SPDIF

#define IMX952_CLK_SPDIF   (IMX952_CCM_NUM_CLK_SRC + 110)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

S/PDIF clock.

◆ IMX952_CLK_SWOTRACE

#define IMX952_CLK_SWOTRACE   (IMX952_CCM_NUM_CLK_SRC + 111)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

SWO trace clock.

◆ IMX952_CLK_TPM2

#define IMX952_CLK_TPM2   (IMX952_CCM_NUM_CLK_SRC + 19)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

TPM2 clock.

◆ IMX952_CLK_TPM4

#define IMX952_CLK_TPM4   (IMX952_CCM_NUM_CLK_SRC + 112)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

TPM4 clock.

◆ IMX952_CLK_TPM5

#define IMX952_CLK_TPM5   (IMX952_CCM_NUM_CLK_SRC + 113)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

TPM5 clock.

◆ IMX952_CLK_TPM6

#define IMX952_CLK_TPM6   (IMX952_CCM_NUM_CLK_SRC + 114)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

TPM6 clock.

◆ IMX952_CLK_TSTMR2

#define IMX952_CLK_TSTMR2   (IMX952_CCM_NUM_CLK_SRC + 115)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Timestamp timer 2 clock.

◆ IMX952_CLK_USBPHYBURUNIN

#define IMX952_CLK_USBPHYBURUNIN   (IMX952_CCM_NUM_CLK_SRC + 116)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

USB PHY burn-in clock.

◆ IMX952_CLK_USDHC1

#define IMX952_CLK_USDHC1   (IMX952_CCM_NUM_CLK_SRC + 117)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

uSDHC1 clock

◆ IMX952_CLK_USDHC2

#define IMX952_CLK_USDHC2   (IMX952_CCM_NUM_CLK_SRC + 118)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

uSDHC2 clock

◆ IMX952_CLK_USDHC3

#define IMX952_CLK_USDHC3   (IMX952_CCM_NUM_CLK_SRC + 119)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

uSDHC3 clock

◆ IMX952_CLK_V2XPK

#define IMX952_CLK_V2XPK   (IMX952_CCM_NUM_CLK_SRC + 120)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

V2X packet engine clock.

◆ IMX952_CLK_VPU

#define IMX952_CLK_VPU   (IMX952_CCM_NUM_CLK_SRC + 74)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Video processing unit clock.

◆ IMX952_CLK_VPUAPB

#define IMX952_CLK_VPUAPB   (IMX952_CCM_NUM_CLK_SRC + 73)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

VPU APB clock.

◆ IMX952_CLK_WAKEUPAXI

#define IMX952_CLK_WAKEUPAXI   (IMX952_CCM_NUM_CLK_SRC + 121)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

Wakeup AXI clock.

◆ IMX952_CLK_XSPI1

#define IMX952_CLK_XSPI1   (IMX952_CCM_NUM_CLK_SRC + 85)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

eXecute-in-place SPI 1 clock

◆ IMX952_CLK_XSPISLVROOT

#define IMX952_CLK_XSPISLVROOT   (IMX952_CCM_NUM_CLK_SRC + 122)

#include <zephyr/dt-bindings/clock/imx952_clock.h>

XPI slave root clock.