CH32 reset controller helpers

Macros for encoding CH32 peripheral reset cells. More...

Files
file	ch32-common.h
	CH32 reset controller devicetree common helper macros.
file	ch32v00x-reset.h
	CH32 reset controller devicetree helper macros for CH32V00X.
file	ch32v20x_30x-reset.h
	CH32 reset controller devicetree helper macros for CH32V20X-V30X.

Macros
#define	CH32_RESET(bus, bit)
	Encode a peripheral reset cell value for the wch,ch32-rcc-rctl binding.

Detailed Description

Macros for encoding CH32 peripheral reset cells.

Devicetree macro for encoding peripheral reset on CH32 devices, for use with the wch,ch32-rcc-rctl compatible reset controller.

Each SoC family header (for example ch32v20x_30x-reset.h) defines the RCC bus reset register offsets for that family as CH32_RESET_BUS_<bus> constants. A peripheral reset cell is the encoded with CH32_RESET() by combining a bus constant with the bit position of the peripheral's reset line within that bus reset register.

#include <zephyr/dt-bindings/reset/ch32v20x_30x-reset.h>
 
&usart1 {
        resets = <&rctl CH32_RESET(APB2, 14)>;
}

Macro Definition Documentation

CH32_RESET

#define CH32_RESET	(		bus,
			bit )

#include <zephyr/dt-bindings/reset/ch32-common.h>

Value:

(((CH32_RESET_BUS_##bus) << 5U) | (bit))

Encode a peripheral reset cell value for the wch,ch32-rcc-rctl binding.

Packs an RCC bus register offest and a bit position into one 32-bit reset cell value.

Bits [4:0] hold the reset bit position within the 32-bit RCC bus register; bits [16:5] hold the RCC register byte offset relative to the RCC base address.

Parameters

bus	RCC bus name.
bit	Bit position of the peripheral's reset line within the bus reset register.