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Zephyr API Documentation 4.4.99
A Scalable Open Source RTOS
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Macros for encoding GD32 peripheral reset cells. More...
Topics | |
| GigaDevice GD32A50x reset controller helpers | |
| GigaDevice GD32A50x reset controller helpers. | |
| GigaDevice GD32E10x reset controller helpers | |
| GigaDevice GD32E10x reset controller helpers. | |
| GigaDevice GD32E50x reset controller helpers | |
| GigaDevice GD32E50x reset controller helpers. | |
| GigaDevice GD32F3x0 reset controller helpers | |
| GigaDevice GD32F3x0 reset controller helpers. | |
| GigaDevice GD32F403 reset controller helpers | |
| GigaDevice GD32F403 reset controller helpers. | |
| GigaDevice GD32F4xx reset controller helpers | |
| GigaDevice GD32F4xx reset controller helpers. | |
| GigaDevice GD32L23x reset controller helpers | |
| GigaDevice GD32L23x reset controller helpers. | |
| GigaDevice GD32VF103 reset controller helpers | |
| GigaDevice GD32VF103 reset controller helpers. | |
Files | |
| file | gd32-common.h |
| GD32 reset controller devicetree helper macros. | |
Macros for encoding GD32 peripheral reset cells.
Devicetree macros for encoding peripheral reset cells on GigaDevice GD32 devices, for use with the gd,gd32-rctl compatible reset controller.
Each SoC family header (for example gd32f4xx.h) defines RCU reset register offsets for that family and peripheral reset identifiers as GD32_RESET_<peripheral> constants. A peripheral reset cell is encoded by combining an RCU register offset with the bit position of the peripheral's reset line within that register.